/** @file\r
- ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049B\r
+ ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049D\r
\r
- http://infocenter.arm.com/help/topic/com.arm.doc.den0049b/DEN0049B_IO_Remapping_Table.pdf\r
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0049d/DEN0049D_IO_Remapping_Table.pdf\r
\r
Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r
+ Copyright (c) 2018, ARM Limited. All rights reserved.<BR>\r
\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#ifndef __IO_REMAPPING_TABLE_H__\r
#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r
#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r
#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r
+#define EFI_ACPI_IORT_TYPE_PMCG 0x5\r
\r
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3\r
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4\r
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r
\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1\r
+#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3\r
+\r
+#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0\r
+#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1\r
+#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1\r
\r
UINT32 AtsAttribute;\r
UINT32 PciSegmentNumber;\r
+ UINT8 MemoryAddressSize;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r
\r
///\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r
\r
///\r
-/// Node type 4: SMMUv4 node\r
+/// Node type 4: SMMUv3 node\r
///\r
typedef struct {\r
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
UINT32 Pri;\r
UINT32 Gerr;\r
UINT32 Sync;\r
+ UINT32 ProximityDomain;\r
+ UINT32 DeviceIdMappingIndex;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r
\r
+///\r
+/// Node type 5: PMCG node\r
+///\r
+typedef struct {\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+\r
+ UINT64 Base;\r
+ UINT32 OverflowInterruptGsiv;\r
+ UINT32 NodeReference;\r
+ UINT64 Page1Base;\r
+//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r
+} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r
+\r
#pragma pack()\r
\r
#endif\r