/** @file\r
Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.\r
\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
///< be enabled or disabled by\r
///< PAL_PROC_SET_FEATURES. The\r
///< corresponding argument is ignored.\r
- \r
+\r
UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins\r
///< present. Denotes the absence of INIT,\r
///< PMI, LINT0 and LINT1 pins on the\r
///< enabled or disabled by\r
///< PAL_PROC_SET_FEATURES. The corresponding\r
///< argument is ignored.\r
- \r
+\r
UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple\r
///< implementation of\r
///< unimplemented instruction\r
///< bit has no effect if BERR\r
///< signalling is disabled. (See\r
///< PAL_BUS_GET/SET_FEATURES)\r
- \r
+\r
UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When\r
///< 1, the Bus Error (BERR) signal is\r
///< promoted to the Bus Initialization\r
\r
UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the\r
///< instruction cache.\r
- \r
+\r
UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache\r
///< line is held shared. 2 - cache line is held\r
///< exclusive. 3 - cache line is modified. All other\r
///< values are reserved.\r
- \r
+\r
UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check\r
///< parameter is valid.\r
- \r
+\r
UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of\r
///< the cache indicated by this value.\r
\r
///< ignored or generate an illegal argument in\r
///< procedure calls if the caller sets these\r
///< bits.\r
- \r
+\r
UINT64 ControlSupport:1; ///< This bit defines if an implementation\r
///< supports control of the PAL self-tests\r
///< via the self-test control word. If\r