/** @file\r
Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
/**\r
PAL Procedure - PAL_CACHE_FLUSH.\r
\r
- Flush the instruction or data caches. It is required by IPF.\r
+ Flush the instruction or data caches. It is required by Itanium processors.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at virtual mode and physical\r
mode.\r
PAL Procedure - PAL_CACHE_INFO.\r
\r
Return detailed instruction or data cache information. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at virtual\r
mode and physical mode.\r
\r
PAL Procedure - PAL_CACHE_INIT.\r
\r
Initialize the instruction or data caches. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_CACHE_INIT within the list of PAL\r
PAL Procedure - PAL_CACHE_PROT_INFO.\r
\r
Return instruction or data cache protection information. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and Virtual mode.\r
\r
PAL Procedure - PAL_CACHE_SUMMARY.\r
\r
Return a summary of the cache hierarchy. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and Virtual\r
mode.\r
\r
PAL Procedure - PAL_MEM_ATTRIB.\r
\r
Return a list of supported memory attributes.. It is required\r
- by IPF. The PAL procedure supports the Static Registers calling\r
+ by Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and Virtual\r
mode.\r
\r
\r
Used in architected sequence to transition pages from a\r
cacheable, speculative attribute to an uncacheable attribute.\r
- It is required by IPF. The PAL procedure supports the Static\r
+ It is required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and Virtual mode.\r
\r
PAL Procedure - PAL_PTCE_INFO.\r
\r
Return information needed for ptc.e instruction to purge\r
- entire TC. It is required by IPF. The PAL procedure supports\r
+ entire TC. It is required by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_INFO.\r
\r
Return detailed information about virtual memory features\r
- supported in the processor. It is required by IPF. The PAL\r
+ supported in the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_PAGE_SIZE.\r
\r
Return virtual memory TC and hardware walker page sizes\r
- supported in the processor. It is required by IPF. The PAL\r
+ supported in the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_SUMMARY.\r
\r
Return summary information about virtual memory features\r
- supported in the processor. It is required by IPF. The PAL\r
+ supported in the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
PAL Procedure - PAL_VM_TR_READ.\r
\r
Read contents of a translation register. It is required by\r
- IPF. The PAL procedure supports the Stacked Register calling\r
+ Itanium processors. The PAL procedure supports the Stacked Register calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_VM_TR_READ within the list\r
PAL Procedure - PAL_BUS_GET_FEATURES.\r
\r
Return configurable processor bus interface features and their\r
- current settings. It is required by IPF. The PAL procedure\r
+ current settings. It is required by Itanium processors. The PAL procedure\r
supports the Stacked Register calling convention. It could be\r
called at physical mode.\r
\r
PAL Procedure - PAL_BUS_SET_FEATURES.\r
\r
Enable or disable configurable features in processor bus\r
- interface. It is required by IPF. It is required by IPF. The PAL procedure\r
+ interface. It is required by Itanium processors. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode.\r
\r
PAL Procedure - PAL_DEBUG_INFO.\r
\r
Return the number of instruction and data breakpoint\r
- registers. It is required by IPF. It is required by IPF. The\r
+ registers. It is required by Itanium processors. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
PAL Procedure - PAL_FIXED_ADDR.\r
\r
Return the fixed component of a processor's directed address.\r
- It is required by IPF. It is required by IPF. The PAL\r
+ It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
\r
Return ratio of processor, bus, and interval time counter to\r
processor input clock or output clock for platform use, if\r
- generated by the processor. It is required by IPF. The PAL\r
+ generated by the processor. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
PAL Procedure - PAL_PERF_MON_INFO.\r
\r
Return the number and type of performance monitors. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode and virtual mode.\r
\r
PAL Procedure - PAL_PLATFORM_ADDR.\r
\r
Specify processor interrupt block address and I/O port space\r
- address. It is required by IPF. The PAL procedure supports the\r
+ address. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_PROC_GET_FEATURES.\r
\r
Return configurable processor features and their current\r
- setting. It is required by IPF. The PAL procedure supports the\r
+ setting. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_PROC_SET_FEATURES.\r
\r
Enable or disable configurable processor features. It is\r
- required by IPF. The PAL procedure supports the Static\r
+ required by Itanium processors. The PAL procedure supports the Static\r
Registers calling convention. It could be called at physical\r
mode.\r
\r
/**\r
PAL Procedure - PAL_REGISTER_INFO.\r
\r
- Return AR and CR register information. It is required by IPF.\r
+ Return AR and CR register information. It is required by Itanium processors.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
/**\r
PAL Procedure - PAL_RSE_INFO.\r
\r
- Return RSE information. It is required by IPF. The PAL\r
+ Return RSE information. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
/**\r
PAL Procedure - PAL_VERSION.\r
\r
- Return version of PAL code. It is required by IPF. The PAL\r
+ Return version of PAL code. It is required by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
PAL Procedure - PAL_MC_CLEAR_LOG.\r
\r
Clear all error information from processor error logging\r
- registers. It is required by IPF. The PAL procedure supports\r
+ registers. It is required by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_MC_DRAIN.\r
\r
Ensure that all operations that could cause an MCA have\r
- completed. It is required by IPF. The PAL procedure supports\r
+ completed. It is required by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical mode and virtual mode.\r
\r
PAL Procedure - PAL_MC_ERROR_INFO.\r
\r
Return Processor Machine Check Information and Processor\r
- Static State for logging by SAL. It is required by IPF. The\r
+ Static State for logging by SAL. It is required by Itanium processors. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
\r
PAL Procedure - PAL_MC_EXPECTED.\r
\r
Set/Reset Expected Machine Check Indicator. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_MC_EXPECTED within the list of PAL\r
PAL Procedure - PAL_MC_REGISTER_MEM.\r
\r
Register min-state save area with PAL for machine checks and\r
- inits. It is required by IPF. The PAL procedure supports the\r
+ inits. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
PAL Procedure - PAL_MC_RESUME.\r
\r
Restore minimal architected state and return to interrupted\r
- process. It is required by IPF. The PAL procedure supports the\r
+ process. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
PAL Procedure - PAL_HALT_INFO.\r
\r
Return the low power capabilities of the processor. It is\r
- required by IPF. The PAL procedure supports the\r
+ required by Itanium processors. The PAL procedure supports the\r
Stacked Registers calling convention. It could be called at\r
physical and virtual mode.\r
\r
PAL Procedure - PAL_HALT_LIGHT.\r
\r
Enter the low power LIGHT HALT state. It is required by\r
- IPF. The PAL procedure supports the Static Registers calling\r
+ Itanium processors. The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
\r
@param Index Index of PAL_HALT_LIGHT within the list of PAL\r
PAL Procedure - PAL_CACHE_LINE_INIT.\r
\r
Initialize tags and data of a cache line for processor\r
- testing. It is required by IPF. The PAL procedure supports the\r
+ testing. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical and virtual mode.\r
\r
Returns alignment and size requirements needed for the memory\r
buffer passed to the PAL_TEST_PROC procedure as well as\r
information on self-test control words for the processor self\r
- tests. It is required by IPF. The PAL procedure supports the\r
+ tests. It is required by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
/**\r
PAL Procedure - PAL_TEST_PROC.\r
\r
- Perform late processor self test. It is required by IPF. The\r
+ Perform late processor self test. It is required by Itanium processors. The\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
PAL Procedure - PAL_COPY_INFO.\r
\r
Return information needed to relocate PAL procedures and PAL\r
- PMI code to memory. It is required by IPF. The PAL procedure\r
+ PMI code to memory. It is required by Itanium processors. The PAL procedure\r
supports the Static Registers calling convention. It could be\r
called at physical mode.\r
\r
PAL Procedure - PAL_COPY_PAL.\r
\r
Relocate PAL procedures and PAL PMI code to memory. It is\r
- required by IPF. The PAL procedure supports the Stacked\r
+ required by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at physical\r
mode.\r
\r
PAL Procedure - PAL_PMI_ENTRYPOINT.\r
\r
Register PMI memory entrypoints with processor. It is required\r
- by IPF. The PAL procedure supports the Stacked Registers\r
+ by Itanium processors. The PAL procedure supports the Stacked Registers\r
calling convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
PAL Procedure - PAL_BRAND_INFO.\r
\r
Provides processor branding information. It is optional by\r
- IPF. The PAL procedure supports the Stacked Registers calling\r
+ Itanium processors. The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at physical and Virtual mode.\r
\r
@param Index Index of PAL_BRAND_INFO within the list of PAL\r
PAL Procedure - PAL_GET_HW_POLICY.\r
\r
Returns the current hardware resource sharing policy of the\r
- processor. It is optional by IPF. The PAL procedure supports\r
+ processor. It is optional by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical and Virtual mode.\r
\r
PAL Procedure - PAL_SET_HW_POLICY.\r
\r
Sets the current hardware resource sharing policy of the\r
- processor. It is optional by IPF. The PAL procedure supports\r
+ processor. It is optional by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called at\r
physical and Virtual mode.\r
\r
\r
Injects the requested processor error or returns information\r
on the supported injection capabilities for this particular\r
- processor implementation. It is optional by IPF. The PAL\r
+ processor implementation. It is optional by Itanium processors. The PAL\r
procedure supports the Stacked Registers calling convention.\r
It could be called at physical and Virtual mode.\r
\r
PAL Procedure - PAL_GET_PSTATE.\r
\r
Returns the performance index of the processor. It is optional\r
- by IPF. The PAL procedure supports the Stacked Registers\r
+ by Itanium processors. The PAL procedure supports the Stacked Registers\r
calling convention. It could be called at physical and Virtual\r
mode.\r
\r
PAL Procedure - PAL_PSTATE_INFO.\r
\r
Returns information about the P-states supported by the\r
- processor. It is optional by IPF. The PAL procedure supports\r
+ processor. It is optional by Itanium processors. The PAL procedure supports\r
the Static Registers calling convention. It could be called\r
at physical and Virtual mode.\r
\r
PAL Procedure - PAL_SET_PSTATE.\r
\r
To request a processor transition to a given P-state. It is\r
- optional by IPF. The PAL procedure supports the Stacked\r
+ optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at physical\r
and Virtual mode.\r
\r
PAL Procedure - PAL_SHUTDOWN.\r
\r
Put the logical processor into a low power state which can be\r
- exited only by a reset event. It is optional by IPF. The PAL\r
+ exited only by a reset event. It is optional by Itanium processors. The PAL\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode.\r
\r
PAL Procedure - PAL_MEMORY_BUFFER.\r
\r
Provides cacheable memory to PAL for exclusive use during\r
- runtime. It is optional by IPF. The PAL procedure supports the\r
+ runtime. It is optional by Itanium processors. The PAL procedure supports the\r
Static Registers calling convention. It could be called at\r
physical mode.\r
\r
PAL Procedure - PAL_VP_CREATE.\r
\r
Initializes a new vpd for the operation of a new virtual\r
- processor in the virtual environment. It is optional by IPF.\r
+ processor in the virtual environment. It is optional by Itanium processors.\r
The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_ENV_INFO.\r
\r
Returns the parameters needed to enter a virtual environment.\r
- It is optional by IPF. The PAL procedure supports the Stacked\r
+ It is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
PAL Procedure - PAL_VP_EXIT_ENV.\r
\r
Allows a logical processor to exit a virtual environment.\r
- It is optional by IPF. The PAL procedure supports the Stacked\r
+ It is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
PAL Procedure - PAL_VP_INIT_ENV.\r
\r
Allows a logical processor to enter a virtual environment. It\r
- is optional by IPF. The PAL procedure supports the Stacked\r
+ is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
\r
Register a different host IVT and/or a different optional\r
virtualization intercept handler for the virtual processor\r
- specified by vpd. It is optional by IPF. The PAL procedure\r
+ specified by vpd. It is optional by Itanium processors. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_RESTORE.\r
\r
Restores virtual processor state for the specified vpd on the\r
- logical processor. It is optional by IPF. The PAL procedure\r
+ logical processor. It is optional by Itanium processors. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_SAVE.\r
\r
Saves virtual processor state for the specified vpd on the\r
- logical processor. It is optional by IPF. The PAL procedure\r
+ logical processor. It is optional by Itanium processors. The PAL procedure\r
supports the Stacked Registers calling convention. It could be\r
called at Virtual mode.\r
\r
PAL Procedure - PAL_VP_TERMINATE.\r
\r
Terminates operation for the specified virtual processor. It\r
- is optional by IPF. The PAL procedure supports the Stacked\r
+ is optional by Itanium processors. The PAL procedure supports the Stacked\r
Registers calling convention. It could be called at Virtual\r
mode.\r
\r
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