MdePkg: Fix ACPI NFIT GUID definitions

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index bf06205bf9026a70a29f213e05160200f9317825..78ec6b316629fc9d876413924011da7dd6c44d50 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -6,7 +6,10 @@
     PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
     PC Card Standard, 8.0\r
 \r
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+  \r
+\r
+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2105, Hewlett-Packard Development Company, L.P.<BR>\r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -219,7 +222,7 @@ typedef struct {
 #define     PCI_IF_16550_MODEM            0x02\r
 #define     PCI_IF_16650_MODEM            0x03\r
 #define     PCI_IF_16750_MODEM            0x04\r
-#define   PCI_SUBCLASS_SCC_OTHER          0x80\r
+#define   PCI_SUBCLASS_SCC_OTHER        0x80\r
 \r
 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08\r
 #define   PCI_SUBCLASS_PIC              0x00\r
@@ -238,7 +241,7 @@ typedef struct {
 #define     PCI_IF_EISA_TIMER             0x02\r
 #define   PCI_SUBCLASS_RTC              0x03\r
 #define     PCI_IF_GENERIC_RTC            0x00\r
-#define     PCI_IF_ISA_RTC                0x00\r
+#define     PCI_IF_ISA_RTC                0x01\r
 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller\r
 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
 \r
@@ -249,10 +252,12 @@ typedef struct {
 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03\r
 #define   PCI_SUBCLASS_GAMEPORT         0x04\r
 #define     PCI_IF_GAMEPORT               0x00\r
-#define     PCI_IF_GAMEPORT1              0x01\r
+#define     PCI_IF_GAMEPORT1              0x10\r
 #define   PCI_SUBCLASS_INPUT_OTHER      0x80\r
 \r
 #define PCI_CLASS_DOCKING_STATION     0x0A\r
+#define   PCI_SUBCLASS_DOCKING_GENERIC  0x00\r
+#define   PCI_SUBCLASS_DOCKING_OTHER    0x80\r
 \r
 #define PCI_CLASS_PROCESSOR           0x0B\r
 #define   PCI_SUBCLASS_PROC_386         0x00\r
@@ -280,7 +285,7 @@ typedef struct {
 #define PCI_CLASS_WIRELESS            0x0D\r
 #define   PCI_SUBCLASS_IRDA             0x00\r
 #define   PCI_SUBCLASS_IR               0x01\r
-#define   PCI_SUBCLASS_RF               0x02\r
+#define   PCI_SUBCLASS_RF               0x10\r
 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80\r
 \r
 #define PCI_CLASS_INTELLIGENT_IO      0x0E\r
@@ -547,6 +552,7 @@ typedef struct {
 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   \r
 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   \r
 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   \r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   \r
 \r
@@ -652,6 +658,42 @@ typedef struct {
   UINT8                   Data;\r
 } EFI_PCI_CAPABILITY_PMI;\r
 \r
+///\r
+/// PMC - Power Management Capabilities\r
+/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+  struct {\r
+    UINT16 Version : 3;\r
+    UINT16 PmeClock : 1;\r
+    UINT16 : 1;\r
+    UINT16 DeviceSpecificInitialization : 1;\r
+    UINT16 AuxCurrent : 3;\r
+    UINT16 D1Support : 1;\r
+    UINT16 D2Support : 1;\r
+    UINT16 PmeSupport : 5;\r
+  } Bits;\r
+  UINT16 Data;\r
+} EFI_PCI_PMC;\r
+\r
+#define EFI_PCI_PMC_D3_COLD_MASK    (BIT15)\r
+\r
+///\r
+/// PMCSR - Power Management Control/Status\r
+/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+  struct {\r
+    UINT16 PowerState : 2;\r
+    UINT16 : 6;\r
+    UINT16 PmeEnable : 1;\r
+    UINT16 DataSelect : 4;\r
+    UINT16 DataScale : 2;\r
+    UINT16 PmeStatus : 1;\r
+  } Bits;\r
+  UINT16 Data;\r
+} EFI_PCI_PMCSR;\r
+\r
 ///\r
 /// A.G.P Capability\r
 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r