+#define PCI_POWER_STATE_D0 0\r
+#define PCI_POWER_STATE_D1 1\r
+#define PCI_POWER_STATE_D2 2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 6;\r
+ UINT8 B2B3 : 1;\r
+ UINT8 BusPowerClockControl : 1;\r
+ } Bits;\r
+ UINT8 Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ EFI_PCI_PMC PMC;\r
+ EFI_PCI_PMCSR PMCSR;\r
+ EFI_PCI_PMCSR_BSE BridgeExtention;\r
+ UINT8 Data;\r
+} EFI_PCI_CAPABILITY_PMI;\r
+\r