UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci23.h

diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index 72571028c655b1f1aa92cea8a47ebdea0835d5c0..1c43d041b04b69116d52fbdbe32cae808b52a9eb 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -1,26 +1,127 @@
 /** @file\r
   Support for PCI 2.3 standard.\r
 \r
-  Copyright (c) 2006, Intel Corporation                                                         \r
-  All rights reserved. This program and the accompanying materials                          \r
-  are licensed and made available under the terms and conditions of the BSD License         \r
-  which accompanies this distribution.  The full text of the license may be found at        \r
-  http://opensource.org/licenses/bsd-license.php                                            \r
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+**/\r
 \r
-  Module Name:  pci23.h\r
+#ifndef _PCI23_H_\r
+#define _PCI23_H_\r
 \r
-**/\r
+#include <IndustryStandard/Pci22.h>\r
 \r
-#ifndef _PCI23_H\r
-#define _PCI23_H\r
+///\r
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
+///\r
+///@{\r
+#define PCI_CLASS_MASS_STORAGE_ATA         0x05\r
+#define   PCI_IF_MASS_STORAGE_SINGLE_DMA   0x20\r
+#define   PCI_IF_MASS_STORAGE_CHAINED_DMA  0x30\r
+///@}\r
 \r
+///\r
+/// PCI_CLASS_NETWORK, Base Class 02h.\r
+///\r
+///@{\r
+#define PCI_CLASS_NETWORK_WORLDFIP               0x05\r
+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING  0x06\r
+///@}\r
 \r
-#define PCI_EXP_MAX_CONFIG_OFFSET     0x1000\r
-#define EFI_PCI_CAPABILITY_ID_PCIEXP  0x10\r
+///\r
+/// PCI_CLASS_BRIDGE, Base Class 06h.\r
+///\r
+///@{\r
+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P           0x09\r
+#define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY    0x40\r
+#define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY  0x80\r
+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI              0x0A\r
+///@}\r
 \r
-#include <IndustryStandard/Pci22.h>\r
+///\r
+/// PCI_CLASS_SCC, Base Class 07h.\r
+///\r
+///@{\r
+#define PCI_SUBCLASS_GPIB        0x04\r
+#define PCI_SUBCLASS_SMART_CARD  0x05\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_SERIAL, Base Class 0Ch.\r
+///\r
+///@{\r
+#define   PCI_IF_EHCI            0x20\r
+#define PCI_CLASS_SERIAL_IB      0x06\r
+#define PCI_CLASS_SERIAL_IPMI    0x07\r
+#define   PCI_IF_IPMI_SMIC       0x00\r
+#define   PCI_IF_IPMI_KCS        0x01           ///< Keyboard Controller Style\r
+#define   PCI_IF_IPMI_BT         0x02           ///< Block Transfer\r
+#define PCI_CLASS_SERIAL_SERCOS  0x08\r
+#define PCI_CLASS_SERIAL_CANBUS  0x09\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_WIRELESS, Base Class 0Dh.\r
+///\r
+///@{\r
+#define PCI_SUBCLASS_BLUETOOTH  0x11\r
+#define PCI_SUBCLASS_BROADBAND  0x12\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_DPIO, Base Class 11h.\r
+///\r
+///@{\r
+#define PCI_SUBCLASS_PERFORMANCE_COUNTERS           0x01\r
+#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION  0x10\r
+#define PCI_SUBCLASS_MANAGEMENT_CARD                0x20\r
+///@}\r
+\r
+///\r
+/// defined in PCI Express Spec.\r
+///\r
+#define PCI_EXP_MAX_CONFIG_OFFSET  0x1000\r
+\r
+///\r
+/// PCI Capability List IDs and records.\r
+///\r
+#define EFI_PCI_CAPABILITY_ID_PCIX    0x07\r
+#define EFI_PCI_CAPABILITY_ID_VENDOR  0x09\r
+\r
+#pragma pack(1)\r
+///\r
+/// PCI-X Capabilities List,\r
+/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR    Hdr;\r
+  UINT16                    CommandReg;\r
+  UINT32                    StatusReg;\r
+} EFI_PCI_CAPABILITY_PCIX;\r
+\r
+///\r
+/// PCI-X Bridge Capabilities List,\r
+/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR    Hdr;\r
+  UINT16                    SecStatusReg;\r
+  UINT32                    StatusReg;\r
+  UINT32                    SplitTransCtrlRegUp;\r
+  UINT32                    SplitTransCtrlRegDn;\r
+} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
+\r
+///\r
+/// Vendor Specific Capability Header\r
+/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR    Hdr;\r
+  UINT8                     Length;\r
+} EFI_PCI_CAPABILITY_VENDOR_HDR;\r
+\r
+#pragma pack()\r
+\r
+#define PCI_CODE_TYPE_EFI_IMAGE  0x03\r
 \r
 #endif\r