Grammatical and disclaimer changes (does not follow internal C coding stds.)

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci23.h

diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index e1289f75c610127546ead10bf64e07197afd55d6..d9ad8ea0171307f6c7d7d5361bd202fb11fedece 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -1,11 +1,11 @@
 /** @file\r
   Support for PCI 2.3 standard.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
+  Copyright (c) 2006 - 2010, Intel Corporation.  All rights reserved<BR>                                                         \r
   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
-  http://opensource.org/licenses/bsd-license.php                                            \r
+  http://opensource.org/licenses/bsd-license.php.                                            \r
 \r
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
@@ -18,23 +18,36 @@
 #include <IndustryStandard/Pci22.h>\r
 \r
 ///\r
-/// Definitions of PCI class bytes and manipulation macros.\r
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
 ///\r
-#define PCI_IF_EHCI                   0x20\r
+///@{\r
+#define PCI_CLASS_MASS_STORAGE_ATA       0x05\r
+#define   PCI_IF_MASS_STORAGE_SINGLE_DMA   0x20\r
+#define   PCI_IF_MASS_STORAGE_CHAINED_DMA  0x30\r
+///@}\r
+\r
+///\r
+/// PCI_CLASS_SERIAL, Base Class 0Ch.\r
+///\r
+///@{\r
+#define   PCI_IF_EHCI                      0x20\r
+#define PCI_CLASS_SERIAL_IB              0x06\r
+///@}\r
 \r
 ///\r
 /// defined in PCI Express Spec.\r
 ///\r
 #define PCI_EXP_MAX_CONFIG_OFFSET     0x1000\r
 \r
-//\r
-// PCI Capability List IDs and records\r
-//\r
+///\r
+/// PCI Capability List IDs and records.\r
+///\r
 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07\r
 \r
 #pragma pack(1)\r
 ///\r
-/// Capability EFI_PCI_CAPABILITY_ID_PCIX, defined in PCI-X Addendum to the PCI Local Bus Specification\r
+/// PCI-X Capabilities List, \r
+/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -42,8 +55,9 @@ typedef struct {
   UINT32                  StatusReg;\r
 } EFI_PCI_CAPABILITY_PCIX;\r
 \r
-/// \r
-/// Capability EFI_PCI_CAPABILITY_PCIX_BRDG, defined in PCI-X Addendum to the PCI Local Bus Specification\r
+///\r
+/// PCI-X Bridge Capabilities List, \r
+/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r