@return The encode ECAM address.\r
\r
**/\r
-#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \\r
+#define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \\r
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
#pragma pack(1)\r
///\r
typedef union {\r
struct {\r
- UINT16 Version : 4;\r
- UINT16 DevicePortType : 4;\r
- UINT16 SlotImplemented : 1;\r
- UINT16 InterruptMessageNumber : 5;\r
- UINT16 Undefined : 1;\r
- UINT16 Reserved : 1;\r
+ UINT16 Version : 4;\r
+ UINT16 DevicePortType : 4;\r
+ UINT16 SlotImplemented : 1;\r
+ UINT16 InterruptMessageNumber : 5;\r
+ UINT16 Undefined : 1;\r
+ UINT16 Reserved : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_CAPABILITY;\r
\r
-#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r
-#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r
-#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r
-#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r
-#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r
-#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r
-#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r
-#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
-#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r
\r
typedef union {\r
struct {\r
- UINT32 MaxPayloadSize : 3;\r
- UINT32 PhantomFunctions : 2;\r
- UINT32 ExtendedTagField : 1;\r
- UINT32 EndpointL0sAcceptableLatency : 3;\r
- UINT32 EndpointL1AcceptableLatency : 3;\r
- UINT32 Undefined : 3;\r
- UINT32 RoleBasedErrorReporting : 1;\r
- UINT32 Reserved : 2;\r
- UINT32 CapturedSlotPowerLimitValue : 8;\r
- UINT32 CapturedSlotPowerLimitScale : 2;\r
- UINT32 FunctionLevelReset : 1;\r
- UINT32 Reserved2 : 3;\r
+ UINT32 MaxPayloadSize : 3;\r
+ UINT32 PhantomFunctions : 2;\r
+ UINT32 ExtendedTagField : 1;\r
+ UINT32 EndpointL0sAcceptableLatency : 3;\r
+ UINT32 EndpointL1AcceptableLatency : 3;\r
+ UINT32 Undefined : 3;\r
+ UINT32 RoleBasedErrorReporting : 1;\r
+ UINT32 Reserved : 2;\r
+ UINT32 CapturedSlotPowerLimitValue : 8;\r
+ UINT32 CapturedSlotPowerLimitScale : 2;\r
+ UINT32 FunctionLevelReset : 1;\r
+ UINT32 Reserved2 : 3;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_DEVICE_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 CorrectableError : 1;\r
- UINT16 NonFatalError : 1;\r
- UINT16 FatalError : 1;\r
- UINT16 UnsupportedRequest : 1;\r
- UINT16 RelaxedOrdering : 1;\r
- UINT16 MaxPayloadSize : 3;\r
- UINT16 ExtendedTagField : 1;\r
- UINT16 PhantomFunctions : 1;\r
- UINT16 AuxPower : 1;\r
- UINT16 NoSnoop : 1;\r
- UINT16 MaxReadRequestSize : 3;\r
- UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
+ UINT16 CorrectableError : 1;\r
+ UINT16 NonFatalError : 1;\r
+ UINT16 FatalError : 1;\r
+ UINT16 UnsupportedRequest : 1;\r
+ UINT16 RelaxedOrdering : 1;\r
+ UINT16 MaxPayloadSize : 3;\r
+ UINT16 ExtendedTagField : 1;\r
+ UINT16 PhantomFunctions : 1;\r
+ UINT16 AuxPower : 1;\r
+ UINT16 NoSnoop : 1;\r
+ UINT16 MaxReadRequestSize : 3;\r
+ UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_DEVICE_CONTROL;\r
\r
#define PCIE_MAX_PAYLOAD_SIZE_128B 0\r
#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6\r
#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7\r
\r
-#define PCIE_MAX_READ_REQ_SIZE_128B 0\r
-#define PCIE_MAX_READ_REQ_SIZE_256B 1\r
-#define PCIE_MAX_READ_REQ_SIZE_512B 2\r
-#define PCIE_MAX_READ_REQ_SIZE_1024B 3\r
-#define PCIE_MAX_READ_REQ_SIZE_2048B 4\r
-#define PCIE_MAX_READ_REQ_SIZE_4096B 5\r
-#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6\r
-#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7\r
+#define PCIE_MAX_READ_REQ_SIZE_128B 0\r
+#define PCIE_MAX_READ_REQ_SIZE_256B 1\r
+#define PCIE_MAX_READ_REQ_SIZE_512B 2\r
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3\r
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4\r
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7\r
\r
typedef union {\r
struct {\r
- UINT16 CorrectableError : 1;\r
- UINT16 NonFatalError : 1;\r
- UINT16 FatalError : 1;\r
- UINT16 UnsupportedRequest : 1;\r
- UINT16 AuxPower : 1;\r
- UINT16 TransactionsPending : 1;\r
- UINT16 Reserved : 10;\r
+ UINT16 CorrectableError : 1;\r
+ UINT16 NonFatalError : 1;\r
+ UINT16 FatalError : 1;\r
+ UINT16 UnsupportedRequest : 1;\r
+ UINT16 AuxPower : 1;\r
+ UINT16 TransactionsPending : 1;\r
+ UINT16 Reserved : 10;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_DEVICE_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 MaxLinkSpeed : 4;\r
- UINT32 MaxLinkWidth : 6;\r
- UINT32 Aspm : 2;\r
- UINT32 L0sExitLatency : 3;\r
- UINT32 L1ExitLatency : 3;\r
- UINT32 ClockPowerManagement : 1;\r
- UINT32 SurpriseDownError : 1;\r
- UINT32 DataLinkLayerLinkActive : 1;\r
- UINT32 LinkBandwidthNotification : 1;\r
- UINT32 AspmOptionalityCompliance : 1;\r
- UINT32 Reserved : 1;\r
- UINT32 PortNumber : 8;\r
+ UINT32 MaxLinkSpeed : 4;\r
+ UINT32 MaxLinkWidth : 6;\r
+ UINT32 Aspm : 2;\r
+ UINT32 L0sExitLatency : 3;\r
+ UINT32 L1ExitLatency : 3;\r
+ UINT32 ClockPowerManagement : 1;\r
+ UINT32 SurpriseDownError : 1;\r
+ UINT32 DataLinkLayerLinkActive : 1;\r
+ UINT32 LinkBandwidthNotification : 1;\r
+ UINT32 AspmOptionalityCompliance : 1;\r
+ UINT32 Reserved : 1;\r
+ UINT32 PortNumber : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_LINK_CAPABILITY;\r
\r
-#define PCIE_LINK_ASPM_L0S BIT0\r
-#define PCIE_LINK_ASPM_L1 BIT1\r
+#define PCIE_LINK_ASPM_L0S BIT0\r
+#define PCIE_LINK_ASPM_L1 BIT1\r
\r
typedef union {\r
struct {\r
- UINT16 AspmControl : 2;\r
- UINT16 Reserved : 1;\r
- UINT16 ReadCompletionBoundary : 1;\r
- UINT16 LinkDisable : 1;\r
- UINT16 RetrainLink : 1;\r
- UINT16 CommonClockConfiguration : 1;\r
- UINT16 ExtendedSynch : 1;\r
- UINT16 ClockPowerManagement : 1;\r
- UINT16 HardwareAutonomousWidthDisable : 1;\r
- UINT16 LinkBandwidthManagementInterrupt : 1;\r
- UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
+ UINT16 AspmControl : 2;\r
+ UINT16 Reserved : 1;\r
+ UINT16 ReadCompletionBoundary : 1;\r
+ UINT16 LinkDisable : 1;\r
+ UINT16 RetrainLink : 1;\r
+ UINT16 CommonClockConfiguration : 1;\r
+ UINT16 ExtendedSynch : 1;\r
+ UINT16 ClockPowerManagement : 1;\r
+ UINT16 HardwareAutonomousWidthDisable : 1;\r
+ UINT16 LinkBandwidthManagementInterrupt : 1;\r
+ UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 CurrentLinkSpeed : 4;\r
- UINT16 NegotiatedLinkWidth : 6;\r
- UINT16 Undefined : 1;\r
- UINT16 LinkTraining : 1;\r
- UINT16 SlotClockConfiguration : 1;\r
- UINT16 DataLinkLayerLinkActive : 1;\r
- UINT16 LinkBandwidthManagement : 1;\r
- UINT16 LinkAutonomousBandwidth : 1;\r
+ UINT16 CurrentLinkSpeed : 4;\r
+ UINT16 NegotiatedLinkWidth : 6;\r
+ UINT16 Undefined : 1;\r
+ UINT16 LinkTraining : 1;\r
+ UINT16 SlotClockConfiguration : 1;\r
+ UINT16 DataLinkLayerLinkActive : 1;\r
+ UINT16 LinkBandwidthManagement : 1;\r
+ UINT16 LinkAutonomousBandwidth : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 AttentionButton : 1;\r
- UINT32 PowerController : 1;\r
- UINT32 MrlSensor : 1;\r
- UINT32 AttentionIndicator : 1;\r
- UINT32 PowerIndicator : 1;\r
- UINT32 HotPlugSurprise : 1;\r
- UINT32 HotPlugCapable : 1;\r
- UINT32 SlotPowerLimitValue : 8;\r
- UINT32 SlotPowerLimitScale : 2;\r
- UINT32 ElectromechanicalInterlock : 1;\r
- UINT32 NoCommandCompleted : 1;\r
- UINT32 PhysicalSlotNumber : 13;\r
+ UINT32 AttentionButton : 1;\r
+ UINT32 PowerController : 1;\r
+ UINT32 MrlSensor : 1;\r
+ UINT32 AttentionIndicator : 1;\r
+ UINT32 PowerIndicator : 1;\r
+ UINT32 HotPlugSurprise : 1;\r
+ UINT32 HotPlugCapable : 1;\r
+ UINT32 SlotPowerLimitValue : 8;\r
+ UINT32 SlotPowerLimitScale : 2;\r
+ UINT32 ElectromechanicalInterlock : 1;\r
+ UINT32 NoCommandCompleted : 1;\r
+ UINT32 PhysicalSlotNumber : 13;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_SLOT_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 AttentionButtonPressed : 1;\r
- UINT16 PowerFaultDetected : 1;\r
- UINT16 MrlSensorChanged : 1;\r
- UINT16 PresenceDetectChanged : 1;\r
- UINT16 CommandCompletedInterrupt : 1;\r
- UINT16 HotPlugInterrupt : 1;\r
- UINT16 AttentionIndicator : 2;\r
- UINT16 PowerIndicator : 2;\r
- UINT16 PowerController : 1;\r
- UINT16 ElectromechanicalInterlock : 1;\r
- UINT16 DataLinkLayerStateChanged : 1;\r
- UINT16 Reserved : 3;\r
+ UINT16 AttentionButtonPressed : 1;\r
+ UINT16 PowerFaultDetected : 1;\r
+ UINT16 MrlSensorChanged : 1;\r
+ UINT16 PresenceDetectChanged : 1;\r
+ UINT16 CommandCompletedInterrupt : 1;\r
+ UINT16 HotPlugInterrupt : 1;\r
+ UINT16 AttentionIndicator : 2;\r
+ UINT16 PowerIndicator : 2;\r
+ UINT16 PowerController : 1;\r
+ UINT16 ElectromechanicalInterlock : 1;\r
+ UINT16 DataLinkLayerStateChanged : 1;\r
+ UINT16 Reserved : 3;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_SLOT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 AttentionButtonPressed : 1;\r
- UINT16 PowerFaultDetected : 1;\r
- UINT16 MrlSensorChanged : 1;\r
- UINT16 PresenceDetectChanged : 1;\r
- UINT16 CommandCompleted : 1;\r
- UINT16 MrlSensor : 1;\r
- UINT16 PresenceDetect : 1;\r
- UINT16 ElectromechanicalInterlock : 1;\r
- UINT16 DataLinkLayerStateChanged : 1;\r
- UINT16 Reserved : 7;\r
+ UINT16 AttentionButtonPressed : 1;\r
+ UINT16 PowerFaultDetected : 1;\r
+ UINT16 MrlSensorChanged : 1;\r
+ UINT16 PresenceDetectChanged : 1;\r
+ UINT16 CommandCompleted : 1;\r
+ UINT16 MrlSensor : 1;\r
+ UINT16 PresenceDetect : 1;\r
+ UINT16 ElectromechanicalInterlock : 1;\r
+ UINT16 DataLinkLayerStateChanged : 1;\r
+ UINT16 Reserved : 7;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_SLOT_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT16 SystemErrorOnCorrectableError : 1;\r
- UINT16 SystemErrorOnNonFatalError : 1;\r
- UINT16 SystemErrorOnFatalError : 1;\r
- UINT16 PmeInterrupt : 1;\r
- UINT16 CrsSoftwareVisibility : 1;\r
- UINT16 Reserved : 11;\r
+ UINT16 SystemErrorOnCorrectableError : 1;\r
+ UINT16 SystemErrorOnNonFatalError : 1;\r
+ UINT16 SystemErrorOnFatalError : 1;\r
+ UINT16 PmeInterrupt : 1;\r
+ UINT16 CrsSoftwareVisibility : 1;\r
+ UINT16 Reserved : 11;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_ROOT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 CrsSoftwareVisibility : 1;\r
- UINT16 Reserved : 15;\r
+ UINT16 CrsSoftwareVisibility : 1;\r
+ UINT16 Reserved : 15;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_ROOT_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT32 PmeRequesterId : 16;\r
- UINT32 PmeStatus : 1;\r
- UINT32 PmePending : 1;\r
- UINT32 Reserved : 14;\r
+ UINT32 PmeRequesterId : 16;\r
+ UINT32 PmeStatus : 1;\r
+ UINT32 PmePending : 1;\r
+ UINT32 Reserved : 14;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_ROOT_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 CompletionTimeoutRanges : 4;\r
- UINT32 CompletionTimeoutDisable : 1;\r
- UINT32 AriForwarding : 1;\r
- UINT32 AtomicOpRouting : 1;\r
- UINT32 AtomicOp32Completer : 1;\r
- UINT32 AtomicOp64Completer : 1;\r
- UINT32 Cas128Completer : 1;\r
- UINT32 NoRoEnabledPrPrPassing : 1;\r
- UINT32 LtrMechanism : 1;\r
- UINT32 TphCompleter : 2;\r
- UINT32 LnSystemCLS : 2;\r
- UINT32 TenBitTagCompleterSupported : 1;\r
- UINT32 TenBitTagRequesterSupported : 1;\r
- UINT32 Obff : 2;\r
- UINT32 ExtendedFmtField : 1;\r
- UINT32 EndEndTlpPrefix : 1;\r
- UINT32 MaxEndEndTlpPrefixes : 2;\r
- UINT32 EmergencyPowerReductionSupported : 2;\r
- UINT32 EmergencyPowerReductionInitializationRequired : 1;\r
- UINT32 Reserved3 : 4;\r
- UINT32 FrsSupported : 1;\r
+ UINT32 CompletionTimeoutRanges : 4;\r
+ UINT32 CompletionTimeoutDisable : 1;\r
+ UINT32 AriForwarding : 1;\r
+ UINT32 AtomicOpRouting : 1;\r
+ UINT32 AtomicOp32Completer : 1;\r
+ UINT32 AtomicOp64Completer : 1;\r
+ UINT32 Cas128Completer : 1;\r
+ UINT32 NoRoEnabledPrPrPassing : 1;\r
+ UINT32 LtrMechanism : 1;\r
+ UINT32 TphCompleter : 2;\r
+ UINT32 LnSystemCLS : 2;\r
+ UINT32 TenBitTagCompleterSupported : 1;\r
+ UINT32 TenBitTagRequesterSupported : 1;\r
+ UINT32 Obff : 2;\r
+ UINT32 ExtendedFmtField : 1;\r
+ UINT32 EndEndTlpPrefix : 1;\r
+ UINT32 MaxEndEndTlpPrefixes : 2;\r
+ UINT32 EmergencyPowerReductionSupported : 2;\r
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;\r
+ UINT32 Reserved3 : 4;\r
+ UINT32 FrsSupported : 1;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
\r
-#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r
\r
-#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
-#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r
\r
typedef union {\r
struct {\r
- UINT16 CompletionTimeoutValue : 4;\r
- UINT16 CompletionTimeoutDisable : 1;\r
- UINT16 AriForwarding : 1;\r
- UINT16 AtomicOpRequester : 1;\r
- UINT16 AtomicOpEgressBlocking : 1;\r
- UINT16 IdoRequest : 1;\r
- UINT16 IdoCompletion : 1;\r
- UINT16 LtrMechanism : 1;\r
- UINT16 EmergencyPowerReductionRequest : 1;\r
- UINT16 TenBitTagRequesterEnable : 1;\r
- UINT16 Obff : 2;\r
- UINT16 EndEndTlpPrefixBlocking : 1;\r
+ UINT16 CompletionTimeoutValue : 4;\r
+ UINT16 CompletionTimeoutDisable : 1;\r
+ UINT16 AriForwarding : 1;\r
+ UINT16 AtomicOpRequester : 1;\r
+ UINT16 AtomicOpEgressBlocking : 1;\r
+ UINT16 IdoRequest : 1;\r
+ UINT16 IdoCompletion : 1;\r
+ UINT16 LtrMechanism : 1;\r
+ UINT16 EmergencyPowerReductionRequest : 1;\r
+ UINT16 TenBitTagRequesterEnable : 1;\r
+ UINT16 Obff : 2;\r
+ UINT16 EndEndTlpPrefixBlocking : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_DEVICE_CONTROL2;\r
\r
-#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r
-#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r
-#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r
-#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r
-#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r
-#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
-#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r
-#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r
-#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r
-\r
-#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r
-#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
-#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
-#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r
+#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r
+#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r
+#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r
+\r
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 1;\r
- UINT32 LinkSpeedsVector : 7;\r
- UINT32 Crosslink : 1;\r
- UINT32 Reserved2 : 23;\r
+ UINT32 Reserved : 1;\r
+ UINT32 LinkSpeedsVector : 7;\r
+ UINT32 Crosslink : 1;\r
+ UINT32 Reserved2 : 23;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_LINK_CAPABILITY2;\r
\r
typedef union {\r
struct {\r
- UINT16 TargetLinkSpeed : 4;\r
- UINT16 EnterCompliance : 1;\r
- UINT16 HardwareAutonomousSpeedDisable : 1;\r
- UINT16 SelectableDeemphasis : 1;\r
- UINT16 TransmitMargin : 3;\r
- UINT16 EnterModifiedCompliance : 1;\r
- UINT16 ComplianceSos : 1;\r
- UINT16 CompliancePresetDeemphasis : 4;\r
+ UINT16 TargetLinkSpeed : 4;\r
+ UINT16 EnterCompliance : 1;\r
+ UINT16 HardwareAutonomousSpeedDisable : 1;\r
+ UINT16 SelectableDeemphasis : 1;\r
+ UINT16 TransmitMargin : 3;\r
+ UINT16 EnterModifiedCompliance : 1;\r
+ UINT16 ComplianceSos : 1;\r
+ UINT16 CompliancePresetDeemphasis : 4;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_CONTROL2;\r
\r
typedef union {\r
struct {\r
- UINT16 CurrentDeemphasisLevel : 1;\r
- UINT16 EqualizationComplete : 1;\r
- UINT16 EqualizationPhase1Successful : 1;\r
- UINT16 EqualizationPhase2Successful : 1;\r
- UINT16 EqualizationPhase3Successful : 1;\r
- UINT16 LinkEqualizationRequest : 1;\r
- UINT16 Reserved : 10;\r
+ UINT16 CurrentDeemphasisLevel : 1;\r
+ UINT16 EqualizationComplete : 1;\r
+ UINT16 EqualizationPhase1Successful : 1;\r
+ UINT16 EqualizationPhase2Successful : 1;\r
+ UINT16 EqualizationPhase3Successful : 1;\r
+ UINT16 LinkEqualizationRequest : 1;\r
+ UINT16 Reserved : 10;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_STATUS2;\r
\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- PCI_REG_PCIE_CAPABILITY Capability;\r
- PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r
- PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r
- PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r
- PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r
- PCI_REG_PCIE_LINK_CONTROL LinkControl;\r
- PCI_REG_PCIE_LINK_STATUS LinkStatus;\r
- PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r
- PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r
- PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r
- PCI_REG_PCIE_ROOT_CONTROL RootControl;\r
- PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r
- PCI_REG_PCIE_ROOT_STATUS RootStatus;\r
- PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
- PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r
- UINT16 DeviceStatus2;\r
- PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r
- PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r
- PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r
- UINT32 SlotCapability2;\r
- UINT16 SlotControl2;\r
- UINT16 SlotStatus2;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ PCI_REG_PCIE_CAPABILITY Capability;\r
+ PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r
+ PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r
+ PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r
+ PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r
+ PCI_REG_PCIE_LINK_CONTROL LinkControl;\r
+ PCI_REG_PCIE_LINK_STATUS LinkStatus;\r
+ PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r
+ PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r
+ PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r
+ PCI_REG_PCIE_ROOT_CONTROL RootControl;\r
+ PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r
+ PCI_REG_PCIE_ROOT_STATUS RootStatus;\r
+ PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
+ PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r
+ UINT16 DeviceStatus2;\r
+ PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r
+ PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r
+ PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r
+ UINT32 SlotCapability2;\r
+ UINT16 SlotControl2;\r
+ UINT16 SlotStatus2;\r
} PCI_CAPABILITY_PCIEXP;\r
\r
-#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r
+#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r
\r
//\r
// for SR-IOV\r
//\r
-#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r
-#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r
-#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r
+#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r
+#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r
+#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r
\r
typedef struct {\r
- UINT32 CapabilityHeader;\r
- UINT32 Capability;\r
- UINT16 Control;\r
- UINT16 Status;\r
- UINT16 InitialVFs;\r
- UINT16 TotalVFs;\r
- UINT16 NumVFs;\r
- UINT8 FunctionDependencyLink;\r
- UINT8 Reserved0;\r
- UINT16 FirstVFOffset;\r
- UINT16 VFStride;\r
- UINT16 Reserved1;\r
- UINT16 VFDeviceID;\r
- UINT32 SupportedPageSize;\r
- UINT32 SystemPageSize;\r
- UINT32 VFBar[6];\r
- UINT32 VFMigrationStateArrayOffset;\r
+ UINT32 CapabilityHeader;\r
+ UINT32 Capability;\r
+ UINT16 Control;\r
+ UINT16 Status;\r
+ UINT16 InitialVFs;\r
+ UINT16 TotalVFs;\r
+ UINT16 NumVFs;\r
+ UINT8 FunctionDependencyLink;\r
+ UINT8 Reserved0;\r
+ UINT16 FirstVFOffset;\r
+ UINT16 VFStride;\r
+ UINT16 Reserved1;\r
+ UINT16 VFDeviceID;\r
+ UINT32 SupportedPageSize;\r
+ UINT32 SystemPageSize;\r
+ UINT32 VFBar[6];\r
+ UINT32 VFMigrationStateArrayOffset;\r
} SR_IOV_CAPABILITY_REGISTER;\r
\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r
\r
typedef struct {\r
- UINT32 CapabilityId:16;\r
- UINT32 CapabilityVersion:4;\r
- UINT32 NextCapabilityOffset:12;\r
+ UINT32 CapabilityId : 16;\r
+ UINT32 CapabilityVersion : 4;\r
+ UINT32 NextCapabilityOffset : 12;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r
\r
-#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r
+#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
\r
typedef union {\r
struct {\r
- UINT32 Undefined : 1;\r
- UINT32 Reserved : 3;\r
- UINT32 DataLinkProtocolError : 1;\r
- UINT32 SurpriseDownError : 1;\r
- UINT32 Reserved2 : 6;\r
- UINT32 PoisonedTlp : 1;\r
- UINT32 FlowControlProtocolError : 1;\r
- UINT32 CompletionTimeout : 1;\r
- UINT32 CompleterAbort : 1;\r
- UINT32 UnexpectedCompletion : 1;\r
- UINT32 ReceiverOverflow : 1;\r
- UINT32 MalformedTlp : 1;\r
- UINT32 EcrcError : 1;\r
- UINT32 UnsupportedRequestError : 1;\r
- UINT32 AcsVoilation : 1;\r
- UINT32 UncorrectableInternalError : 1;\r
- UINT32 McBlockedTlp : 1;\r
- UINT32 AtomicOpEgressBlocked : 1;\r
- UINT32 TlpPrefixBlockedError : 1;\r
- UINT32 Reserved3 : 6;\r
+ UINT32 Undefined : 1;\r
+ UINT32 Reserved : 3;\r
+ UINT32 DataLinkProtocolError : 1;\r
+ UINT32 SurpriseDownError : 1;\r
+ UINT32 Reserved2 : 6;\r
+ UINT32 PoisonedTlp : 1;\r
+ UINT32 FlowControlProtocolError : 1;\r
+ UINT32 CompletionTimeout : 1;\r
+ UINT32 CompleterAbort : 1;\r
+ UINT32 UnexpectedCompletion : 1;\r
+ UINT32 ReceiverOverflow : 1;\r
+ UINT32 MalformedTlp : 1;\r
+ UINT32 EcrcError : 1;\r
+ UINT32 UnsupportedRequestError : 1;\r
+ UINT32 AcsVoilation : 1;\r
+ UINT32 UncorrectableInternalError : 1;\r
+ UINT32 McBlockedTlp : 1;\r
+ UINT32 AtomicOpEgressBlocked : 1;\r
+ UINT32 TlpPrefixBlockedError : 1;\r
+ UINT32 Reserved3 : 6;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorStatus;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 HeaderLog[4];\r
- UINT32 RootErrorCommand;\r
- UINT32 RootErrorStatus;\r
- UINT16 ErrorSourceIdentification;\r
- UINT16 CorrectableErrorSourceIdentification;\r
- UINT32 TlpPrefixLog[4];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorStatus;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 HeaderLog[4];\r
+ UINT32 RootErrorCommand;\r
+ UINT32 RootErrorStatus;\r
+ UINT16 ErrorSourceIdentification;\r
+ UINT16 CorrectableErrorSourceIdentification;\r
+ UINT32 TlpPrefixLog[4];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r
\r
typedef struct {\r
- UINT32 VcResourceCapability:24;\r
- UINT32 PortArbTableOffset:8;\r
- UINT32 VcResourceControl;\r
- UINT16 Reserved1;\r
- UINT16 VcResourceStatus;\r
+ UINT32 VcResourceCapability : 24;\r
+ UINT32 PortArbTableOffset : 8;\r
+ UINT32 VcResourceControl;\r
+ UINT16 Reserved1;\r
+ UINT16 VcResourceStatus;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 ExtendedVcCount:3;\r
- UINT32 PortVcCapability1:29;\r
- UINT32 PortVcCapability2:24;\r
- UINT32 VcArbTableOffset:8;\r
- UINT16 PortVcControl;\r
- UINT16 PortVcStatus;\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 ExtendedVcCount : 3;\r
+ UINT32 PortVcCapability1 : 29;\r
+ UINT32 PortVcCapability2 : 24;\r
+ UINT32 VcArbTableOffset : 8;\r
+ UINT16 PortVcControl;\r
+ UINT16 PortVcStatus;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT64 SerialNumber;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT64 SerialNumber;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 ElementSelfDescription;\r
- UINT32 Reserved;\r
- UINT32 LinkEntry[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 ElementSelfDescription;\r
+ UINT32 Reserved;\r
+ UINT32 LinkEntry[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 RootComplexLinkCapabilities;\r
- UINT16 RootComplexLinkControl;\r
- UINT16 RootComplexLinkStatus;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 RootComplexLinkCapabilities;\r
+ UINT16 RootComplexLinkControl;\r
+ UINT16 RootComplexLinkStatus;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 DataSelect:8;\r
- UINT32 Reserved:24;\r
- UINT32 Data;\r
- UINT32 PowerBudgetCapability:1;\r
- UINT32 Reserved2:7;\r
- UINT32 Reserved3:24;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 DataSelect : 8;\r
+ UINT32 Reserved : 24;\r
+ UINT32 Data;\r
+ UINT32 PowerBudgetCapability : 1;\r
+ UINT32 Reserved2 : 7;\r
+ UINT32 Reserved3 : 24;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 AcsCapability;\r
- UINT16 AcsControl;\r
- UINT8 EgressControlVectorArray[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 AcsCapability;\r
+ UINT16 AcsControl;\r
+ UINT8 EgressControlVectorArray[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 AssociationBitmap;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 AssociationBitmap;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r
\r
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 VendorSpecificHeader;\r
- UINT8 VendorSpecific[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 VendorSpecificHeader;\r
+ UINT8 VendorSpecific[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT32 RcrbCapabilities;\r
- UINT32 RcrbControl;\r
- UINT32 Reserved;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT32 RcrbCapabilities;\r
+ UINT32 RcrbControl;\r
+ UINT32 Reserved;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 MultiCastCapability;\r
- UINT16 MulticastControl;\r
- UINT64 McBaseAddress;\r
- UINT64 McReceiveAddress;\r
- UINT64 McBlockAll;\r
- UINT64 McBlockUntranslated;\r
- UINT64 McOverlayBar;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 MultiCastCapability;\r
+ UINT16 MulticastControl;\r
+ UINT64 McBaseAddress;\r
+ UINT64 McReceiveAddress;\r
+ UINT64 McBlockAll;\r
+ UINT64 McBlockUntranslated;\r
+ UINT64 McOverlayBar;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved:4;\r
- UINT32 BarSizeCapability:28;\r
+ UINT32 Reserved : 4;\r
+ UINT32 BarSizeCapability : 28;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;\r
\r
-\r
typedef union {\r
struct {\r
- UINT32 BarIndex:3;\r
- UINT32 Reserved:2;\r
- UINT32 ResizableBarNumber:3;\r
- UINT32 BarSize:6;\r
- UINT32 Reserved2:2;\r
- UINT32 BarSizeCapability:16;\r
+ UINT32 BarIndex : 3;\r
+ UINT32 Reserved : 2;\r
+ UINT32 ResizableBarNumber : 3;\r
+ UINT32 BarSize : 6;\r
+ UINT32 Reserved2 : 2;\r
+ UINT32 BarSizeCapability : 16;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r
\r
-#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)\r
+#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 AriCapability;\r
- UINT16 AriControl;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 AriCapability;\r
+ UINT16 AriControl;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 DpaCapability;\r
- UINT32 DpaLatencyIndicator;\r
- UINT16 DpaStatus;\r
- UINT16 DpaControl;\r
- UINT8 DpaPowerAllocationArray[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 DpaCapability;\r
+ UINT32 DpaLatencyIndicator;\r
+ UINT16 DpaStatus;\r
+ UINT16 DpaControl;\r
+ UINT8 DpaPowerAllocationArray[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r
-\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 MaxSnoopLatency;\r
- UINT16 MaxNoSnoopLatency;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 MaxSnoopLatency;\r
+ UINT16 MaxNoSnoopLatency;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 TphRequesterCapability;\r
- UINT32 TphRequesterControl;\r
- UINT16 TphStTable[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 TphRequesterCapability;\r
+ UINT32 TphRequesterControl;\r
+ UINT16 TphStTable[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r
\r
-#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
+#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
\r
#pragma pack()\r
\r
projects / mirror_edk2.git / blobdiff