/** @file\r
Support for the latest PCI standard.\r
\r
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
#ifndef _PCIEXPRESS21_H_\r
#define _PCIEXPRESS21_H_\r
\r
+#include <IndustryStandard/Pci30.h>\r
+\r
+#pragma pack(1)\r
+///\r
+/// PCI Express Capability Structure\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 Version : 4;\r
+ UINT16 DevicePortType : 4;\r
+ UINT16 SlotImplemented : 1;\r
+ UINT16 InterruptMessageNumber : 5;\r
+ UINT16 Undefined : 1;\r
+ UINT16 Reserved : 1;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_CAPABILITY;\r
+\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 MaxPayloadSize : 3;\r
+ UINT32 PhantomFunctions : 2;\r
+ UINT32 ExtendedTagField : 1;\r
+ UINT32 EndpointL0sAcceptableLatency : 3;\r
+ UINT32 EndpointL1AcceptableLatency : 3;\r
+ UINT32 Undefined : 3;\r
+ UINT32 RoleBasedErrorReporting : 1;\r
+ UINT32 Reserved : 2;\r
+ UINT32 CapturedSlotPowerLimitValue : 8;\r
+ UINT32 CapturedSlotPowerLimitScale : 2;\r
+ UINT32 FunctionLevelReset : 1;\r
+ UINT32 Reserved2 : 3;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_REG_PCIE_DEVICE_CAPABILITY;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 CorrectableError : 1;\r
+ UINT16 NonFatalError : 1;\r
+ UINT16 FatalError : 1;\r
+ UINT16 UnsupportedRequest : 1;\r
+ UINT16 RelaxedOrdering : 1;\r
+ UINT16 MaxPayloadSize : 3;\r
+ UINT16 ExtendedTagField : 1;\r
+ UINT16 PhantomFunctions : 1;\r
+ UINT16 AuxPower : 1;\r
+ UINT16 NoSnoop : 1;\r
+ UINT16 MaxReadRequestSize : 3;\r
+ UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_DEVICE_CONTROL;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 CorrectableError : 1;\r
+ UINT16 NonFatalError : 1;\r
+ UINT16 FatalError : 1;\r
+ UINT16 UnsupportedRequest : 1;\r
+ UINT16 AuxPower : 1;\r
+ UINT16 TransactionsPending : 1;\r
+ UINT16 Reserved : 10;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_DEVICE_STATUS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 MaxLinkSpeed : 4;\r
+ UINT32 MaxLinkWidth : 6;\r
+ UINT32 Aspm : 2;\r
+ UINT32 L0sExitLatency : 3;\r
+ UINT32 L1ExitLatency : 3;\r
+ UINT32 ClockPowerManagement : 1;\r
+ UINT32 SurpriseDownError : 1;\r
+ UINT32 DataLinkLayerLinkActive : 1;\r
+ UINT32 LinkBandwidthNotification : 1;\r
+ UINT32 AspmOptionalityCompliance : 1;\r
+ UINT32 Reserved : 1;\r
+ UINT32 PortNumber : 8;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_REG_PCIE_LINK_CAPABILITY;\r
+\r
+#define PCIE_LINK_ASPM_L0S BIT0\r
+#define PCIE_LINK_ASPM_L1 BIT1\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 AspmControl : 2;\r
+ UINT16 Reserved : 1;\r
+ UINT16 ReadCompletionBoundary : 1;\r
+ UINT16 LinkDisable : 1;\r
+ UINT16 RetrainLink : 1;\r
+ UINT16 CommonClockConfiguration : 1;\r
+ UINT16 ExtendedSynch : 1;\r
+ UINT16 ClockPowerManagement : 1;\r
+ UINT16 HardwareAutonomousWidthDisable : 1;\r
+ UINT16 LinkBandwidthManagementInterrupt : 1;\r
+ UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_LINK_CONTROL;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 CurrentLinkSpeed : 4;\r
+ UINT16 NegotiatedLinkWidth : 6;\r
+ UINT16 Undefined : 1;\r
+ UINT16 LinkTraining : 1;\r
+ UINT16 SlotClockConfiguration : 1;\r
+ UINT16 DataLinkLayerLinkActive : 1;\r
+ UINT16 LinkBandwidthManagement : 1;\r
+ UINT16 LinkAutonomousBandwidth : 1;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_LINK_STATUS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 AttentionButton : 1;\r
+ UINT32 PowerController : 1;\r
+ UINT32 MrlSensor : 1;\r
+ UINT32 AttentionIndicator : 1;\r
+ UINT32 PowerIndicator : 1;\r
+ UINT32 HotPlugSurprise : 1;\r
+ UINT32 HotPlugCapable : 1;\r
+ UINT32 SlotPowerLimitValue : 8;\r
+ UINT32 SlotPowerLimitScale : 2;\r
+ UINT32 ElectromechanicalInterlock : 1;\r
+ UINT32 NoCommandCompleted : 1;\r
+ UINT32 PhysicalSlotNumber : 13;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_REG_PCIE_SLOT_CAPABILITY;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 AttentionButtonPressed : 1;\r
+ UINT32 PowerFaultDetected : 1;\r
+ UINT32 MrlSensorChanged : 1;\r
+ UINT32 PresenceDetectChanged : 1;\r
+ UINT32 CommandCompletedInterrupt : 1;\r
+ UINT32 HotPlugInterrupt : 1;\r
+ UINT32 AttentionIndicator : 2;\r
+ UINT32 PowerIndicator : 2;\r
+ UINT32 PowerController : 1;\r
+ UINT32 ElectromechanicalInterlock : 1;\r
+ UINT32 DataLinkLayerStateChanged : 1;\r
+ UINT32 Reserved : 3;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_SLOT_CONTROL;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 AttentionButtonPressed : 1;\r
+ UINT16 PowerFaultDetected : 1;\r
+ UINT16 MrlSensorChanged : 1;\r
+ UINT16 PresenceDetectChanged : 1;\r
+ UINT16 CommandCompleted : 1;\r
+ UINT16 MrlSensor : 1;\r
+ UINT16 PresenceDetect : 1;\r
+ UINT16 ElectromechanicalInterlock : 1;\r
+ UINT16 DataLinkLayerStateChanged : 1;\r
+ UINT16 Reserved : 7;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_SLOT_STATUS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 SystemErrorOnCorrectableError : 1;\r
+ UINT16 SystemErrorOnNonFatalError : 1;\r
+ UINT16 SystemErrorOnFatalError : 1;\r
+ UINT16 PmeInterrupt : 1;\r
+ UINT16 CrsSoftwareVisibility : 1;\r
+ UINT16 Reserved : 11;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_ROOT_CONTROL;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 CrsSoftwareVisibility : 1;\r
+ UINT16 Reserved : 15;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_ROOT_CAPABILITY;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 PmeRequesterId : 16;\r
+ UINT32 PmeStatus : 1;\r
+ UINT32 PmePending : 1;\r
+ UINT32 Reserved : 14;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_REG_PCIE_ROOT_STATUS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 CompletionTimeoutRanges : 4;\r
+ UINT32 CompletionTimeoutDisable : 1;\r
+ UINT32 AriForwarding : 1;\r
+ UINT32 AtomicOpRouting : 1;\r
+ UINT32 AtomicOp32Completer : 1;\r
+ UINT32 AtomicOp64Completer : 1;\r
+ UINT32 Cas128Completer : 1;\r
+ UINT32 NoRoEnabledPrPrPassing : 1;\r
+ UINT32 LtrMechanism : 1;\r
+ UINT32 TphCompleter : 2;\r
+ UINT32 Reserved : 4;\r
+ UINT32 Obff : 2;\r
+ UINT32 ExtendedFmtField : 1;\r
+ UINT32 EndEndTlpPrefix : 1;\r
+ UINT32 MaxEndEndTlpPrefixes : 2;\r
+ UINT32 Reserved2 : 8;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
+\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 CompletionTimeoutValue : 4;\r
+ UINT16 CompletionTimeoutDisable : 1;\r
+ UINT16 AriForwarding : 1;\r
+ UINT16 AtomicOpRequester : 1;\r
+ UINT16 AtomicOpEgressBlocking : 1;\r
+ UINT16 IdoRequest : 1;\r
+ UINT16 IdoCompletion : 1;\r
+ UINT16 LtrMechanism : 2;\r
+ UINT16 Reserved : 2;\r
+ UINT16 Obff : 2;\r
+ UINT16 EndEndTlpPrefixBlocking : 1;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_DEVICE_CONTROL2;\r
+\r
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r
+#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r
+#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r
+#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r
+\r
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 Reserved : 1;\r
+ UINT32 LinkSpeedsVector : 7;\r
+ UINT32 Crosslink : 1;\r
+ UINT32 Reserved2 : 23;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_REG_PCIE_LINK_CAPABILITY2;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 TargetLinkSpeed : 4;\r
+ UINT16 EnterCompliance : 1;\r
+ UINT16 HardwareAutonomousSpeedDisable : 1;\r
+ UINT16 SelectableDeemphasis : 1;\r
+ UINT16 TransmitMargin : 3;\r
+ UINT16 EnterModifiedCompliance : 1;\r
+ UINT16 ComplianceSos : 1;\r
+ UINT16 CompliancePresetDeemphasis : 4;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_LINK_CONTROL2;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 CurrentDeemphasisLevel : 1;\r
+ UINT16 EqualizationComplete : 1;\r
+ UINT16 EqualizationPhase1Successful : 1;\r
+ UINT16 EqualizationPhase2Successful : 1;\r
+ UINT16 EqualizationPhase3Successful : 1;\r
+ UINT16 LinkEqualizationRequest : 1;\r
+ UINT16 Reserved : 10;\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_REG_PCIE_LINK_STATUS2;\r
+\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ PCI_REG_PCIE_CAPABILITY Capability;\r
+ PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r
+ PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r
+ PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r
+ PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r
+ PCI_REG_PCIE_LINK_CONTROL LinkControl;\r
+ PCI_REG_PCIE_LINK_STATUS LinkStatus;\r
+ PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r
+ PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r
+ PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r
+ PCI_REG_PCIE_ROOT_CONTROL RootControl;\r
+ PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r
+ PCI_REG_PCIE_ROOT_STATUS RootStatus;\r
+ PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
+ PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r
+ UINT16 DeviceStatus2;\r
+ PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r
+ PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r
+ PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r
+ UINT32 SlotCapability2;\r
+ UINT16 SlotControl2;\r
+ UINT16 SlotStatus2;\r
+} PCI_CAPABILITY_PCIEXP;\r
+\r
#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
\r
+typedef union {\r
+ struct {\r
+ UINT32 Undefined : 1;\r
+ UINT32 Reserved : 3;\r
+ UINT32 DataLinkProtocolError : 1;\r
+ UINT32 SurpriseDownError : 1;\r
+ UINT32 Reserved2 : 6;\r
+ UINT32 PoisonedTlp : 1;\r
+ UINT32 FlowControlProtocolError : 1;\r
+ UINT32 CompletionTimeout : 1;\r
+ UINT32 CompleterAbort : 1;\r
+ UINT32 UnexpectedCompletion : 1;\r
+ UINT32 ReceiverOverflow : 1;\r
+ UINT32 MalformedTlp : 1;\r
+ UINT32 EcrcError : 1;\r
+ UINT32 UnsupportedRequestError : 1;\r
+ UINT32 AcsVoilation : 1;\r
+ UINT32 UncorrectableInternalError : 1;\r
+ UINT32 McBlockedTlp : 1;\r
+ UINT32 AtomicOpEgressBlocked : 1;\r
+ UINT32 TlpPrefixBlockedError : 1;\r
+ UINT32 Reserved3 : 6;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r
+\r
typedef struct {\r
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 UncorrectableErrorStatus;\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r
UINT32 CorrectableErrorStatus;\r
UINT32 CorrectableErrorMask;\r
UINT32 AdvancedErrorCapabilitiesAndControl;\r
\r
#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
\r
+#pragma pack()\r
+\r
#endif\r
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