MdePkg PciExpress21: PCI_REG_PCIE_DEVICE_CONTROL2 struct has 17 bits

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / PciExpress21.h

diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index ce9c06a7c6d71d2c3252852dd5913d7d61bfebe2..2c07cb560e92aea21d8dda9f9d61c273dbd1a494 100644 (file)
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -1,15 +1,9 @@
 /** @file\r
   Support for the latest PCI standard.\r
 \r
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
-  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  \r
-  This program and the accompanying materials                          \r
-  are licensed and made available under the terms and conditions of the BSD License         \r
-  which accompanies this distribution.  The full text of the license may be found at        \r
-  http://opensource.org/licenses/bsd-license.php                                            \r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -97,6 +91,24 @@ typedef union {
   UINT16   Uint16;\r
 } PCI_REG_PCIE_DEVICE_CONTROL;\r
 \r
+#define PCIE_MAX_PAYLOAD_SIZE_128B   0\r
+#define PCIE_MAX_PAYLOAD_SIZE_256B   1\r
+#define PCIE_MAX_PAYLOAD_SIZE_512B   2\r
+#define PCIE_MAX_PAYLOAD_SIZE_1024B  3\r
+#define PCIE_MAX_PAYLOAD_SIZE_2048B  4\r
+#define PCIE_MAX_PAYLOAD_SIZE_4096B  5\r
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1  6\r
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2  7\r
+\r
+#define PCIE_MAX_READ_REQ_SIZE_128B    0\r
+#define PCIE_MAX_READ_REQ_SIZE_256B    1\r
+#define PCIE_MAX_READ_REQ_SIZE_512B    2\r
+#define PCIE_MAX_READ_REQ_SIZE_1024B   3\r
+#define PCIE_MAX_READ_REQ_SIZE_2048B   4\r
+#define PCIE_MAX_READ_REQ_SIZE_4096B   5\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1   6\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2   7\r
+\r
 typedef union {\r
   struct {\r
     UINT16 CorrectableError : 1;\r
@@ -182,18 +194,18 @@ typedef union {
 \r
 typedef union {\r
   struct {\r
-    UINT32 AttentionButtonPressed : 1;\r
-    UINT32 PowerFaultDetected : 1;\r
-    UINT32 MrlSensorChanged : 1;\r
-    UINT32 PresenceDetectChanged : 1;\r
-    UINT32 CommandCompletedInterrupt : 1;\r
-    UINT32 HotPlugInterrupt : 1;\r
-    UINT32 AttentionIndicator : 2;\r
-    UINT32 PowerIndicator : 2;\r
-    UINT32 PowerController : 1;\r
-    UINT32 ElectromechanicalInterlock : 1;\r
-    UINT32 DataLinkLayerStateChanged : 1;\r
-    UINT32 Reserved : 3;\r
+    UINT16 AttentionButtonPressed : 1;\r
+    UINT16 PowerFaultDetected : 1;\r
+    UINT16 MrlSensorChanged : 1;\r
+    UINT16 PresenceDetectChanged : 1;\r
+    UINT16 CommandCompletedInterrupt : 1;\r
+    UINT16 HotPlugInterrupt : 1;\r
+    UINT16 AttentionIndicator : 2;\r
+    UINT16 PowerIndicator : 2;\r
+    UINT16 PowerController : 1;\r
+    UINT16 ElectromechanicalInterlock : 1;\r
+    UINT16 DataLinkLayerStateChanged : 1;\r
+    UINT16 Reserved : 3;\r
   } Bits;\r
   UINT16   Uint16;\r
 } PCI_REG_PCIE_SLOT_CONTROL;\r
@@ -256,16 +268,30 @@ typedef union {
     UINT32 NoRoEnabledPrPrPassing : 1;\r
     UINT32 LtrMechanism : 1;\r
     UINT32 TphCompleter : 2;\r
-    UINT32 Reserved : 4;\r
+    UINT32 LnSystemCLS : 2;\r
+    UINT32 TenBitTagCompleterSupported : 1;\r
+    UINT32 TenBitTagRequesterSupported : 1;\r
     UINT32 Obff : 2;\r
     UINT32 ExtendedFmtField : 1;\r
     UINT32 EndEndTlpPrefix : 1;\r
     UINT32 MaxEndEndTlpPrefixes : 2;\r
-    UINT32 Reserved2 : 8;\r
+    UINT32 EmergencyPowerReductionSupported : 2;\r
+    UINT32 EmergencyPowerReductionInitializationRequired : 1;\r
+    UINT32 Reserved3 : 4;\r
+    UINT32 FrsSupported : 1;\r
   } Bits;\r
   UINT32   Uint32;\r
 } PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
 \r
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED           0\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED       1\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED       2\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED     3\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED     6\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED   7\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED   14\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r
+\r
 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1\r
 \r
@@ -278,8 +304,9 @@ typedef union {
     UINT16 AtomicOpEgressBlocking : 1;\r
     UINT16 IdoRequest : 1;\r
     UINT16 IdoCompletion : 1;\r
-    UINT16 LtrMechanism : 2;\r
-    UINT16 Reserved : 2;\r
+    UINT16 LtrMechanism : 1;\r
+    UINT16 EmergencyPowerReductionRequest : 1;\r
+    UINT16 TenBitTagRequesterEnable : 1;\r
     UINT16 Obff : 2;\r
     UINT16 EndEndTlpPrefixBlocking : 1;\r
   } Bits;\r