\r
typedef union {\r
struct {\r
- UINT32 PerformEqualization : 1;\r
- UINT32 LinkEqualizationRequestInterruptEnable : 1;\r
- UINT32 Reserved : 30;\r
+ UINT32 PerformEqualization : 1;\r
+ UINT32 LinkEqualizationRequestInterruptEnable : 1;\r
+ UINT32 Reserved : 30;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_LINK_CONTROL3;\r
\r
typedef union {\r
struct {\r
- UINT16 DownstreamPortTransmitterPreset : 4;\r
- UINT16 DownstreamPortReceiverPresetHint : 3;\r
- UINT16 Reserved : 1;\r
- UINT16 UpstreamPortTransmitterPreset : 4;\r
- UINT16 UpstreamPortReceiverPresetHint : 3;\r
- UINT16 Reserved2 : 1;\r
+ UINT16 DownstreamPortTransmitterPreset : 4;\r
+ UINT16 DownstreamPortReceiverPresetHint : 3;\r
+ UINT16 Reserved : 1;\r
+ UINT16 UpstreamPortTransmitterPreset : 4;\r
+ UINT16 UpstreamPortReceiverPresetHint : 3;\r
+ UINT16 Reserved2 : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;\r
- UINT32 LaneErrorStatus;\r
- PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;\r
+ UINT32 LaneErrorStatus;\r
+ PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;\r
\r
#pragma pack()\r