\r
typedef union {\r
struct {\r
- UINT32 PciPmL12 : 1;\r
- UINT32 PciPmL11 : 1;\r
- UINT32 AspmL12 : 1;\r
- UINT32 AspmL11 : 1;\r
- UINT32 L1PmSubstates : 1;\r
- UINT32 Reserved : 3;\r
- UINT32 CommonModeRestoreTime : 8;\r
- UINT32 TPowerOnScale : 2;\r
- UINT32 Reserved2 : 1;\r
- UINT32 TPowerOnValue : 5;\r
- UINT32 Reserved3 : 8;\r
+ UINT32 PciPmL12 : 1;\r
+ UINT32 PciPmL11 : 1;\r
+ UINT32 AspmL12 : 1;\r
+ UINT32 AspmL11 : 1;\r
+ UINT32 L1PmSubstates : 1;\r
+ UINT32 Reserved : 3;\r
+ UINT32 CommonModeRestoreTime : 8;\r
+ UINT32 TPowerOnScale : 2;\r
+ UINT32 Reserved2 : 1;\r
+ UINT32 TPowerOnValue : 5;\r
+ UINT32 Reserved3 : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT32 PciPmL12 : 1;\r
- UINT32 PciPmL11 : 1;\r
- UINT32 AspmL12 : 1;\r
- UINT32 AspmL11 : 1;\r
- UINT32 Reserved : 4;\r
- UINT32 CommonModeRestoreTime : 8;\r
- UINT32 LtrL12ThresholdValue : 10;\r
- UINT32 Reserved2 : 3;\r
- UINT32 LtrL12ThresholdScale : 3;\r
+ UINT32 PciPmL12 : 1;\r
+ UINT32 PciPmL11 : 1;\r
+ UINT32 AspmL12 : 1;\r
+ UINT32 AspmL11 : 1;\r
+ UINT32 Reserved : 4;\r
+ UINT32 CommonModeRestoreTime : 8;\r
+ UINT32 LtrL12ThresholdValue : 10;\r
+ UINT32 Reserved2 : 3;\r
+ UINT32 LtrL12ThresholdScale : 3;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;\r
\r
typedef union {\r
struct {\r
- UINT32 TPowerOnScale : 2;\r
- UINT32 Reserved : 1;\r
- UINT32 TPowerOnValue : 5;\r
- UINT32 Reserved2 : 24;\r
+ UINT32 TPowerOnScale : 2;\r
+ UINT32 Reserved : 1;\r
+ UINT32 TPowerOnValue : 5;\r
+ UINT32 Reserved2 : 24;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\r
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;\r
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\r
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;\r
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;\r
\r
#pragma pack()\r