MdePkg: Apply uncrustify changes

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / PciExpress40.h

diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
index 0564d728618aa8b562e3a18ef02e06b2aa5760aa..2a6a0f20a41230d90adda7c56748d3b8bd6466c4 100644 (file)
--- a/MdePkg/Include/IndustryStandard/PciExpress40.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -24,58 +24,58 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1  0x1\r
 \r
 // Register offsets from Physical Layer PCI-E Ext Cap Header\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET                         0x04\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET                              0x08\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET                               0x0C\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET             0x10\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET     0x14\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET    0x18\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET            0x20\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET                       0x04\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET                            0x08\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET                             0x0C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET           0x10\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET   0x14\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET  0x18\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET          0x20\r
 \r
 typedef union {\r
   struct {\r
-    UINT32 Reserved                  : 32; // Reserved bit 0:31\r
+    UINT32    Reserved : 32;               // Reserved bit 0:31\r
   } Bits;\r
-  UINT32   Uint32;\r
+  UINT32    Uint32;\r
 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r
 \r
 typedef union {\r
   struct {\r
-    UINT32 Reserved                  : 32; // Reserved bit 0:31\r
+    UINT32    Reserved : 32;               // Reserved bit 0:31\r
   } Bits;\r
-  UINT32   Uint32;\r
+  UINT32    Uint32;\r
 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r
 \r
 typedef union {\r
   struct {\r
-    UINT32 EqualizationComplete      : 1; // bit 0\r
-    UINT32 EqualizationPhase1Success : 1; // bit 1\r
-    UINT32 EqualizationPhase2Success : 1; // bit 2\r
-    UINT32 EqualizationPhase3Success : 1; // bit 3\r
-    UINT32 LinkEqualizationRequest   : 1; // bit 4\r
-    UINT32 Reserved                  : 27; // Reserved bit 5:31\r
+    UINT32    EqualizationComplete      : 1;  // bit 0\r
+    UINT32    EqualizationPhase1Success : 1;  // bit 1\r
+    UINT32    EqualizationPhase2Success : 1;  // bit 2\r
+    UINT32    EqualizationPhase3Success : 1;  // bit 3\r
+    UINT32    LinkEqualizationRequest   : 1;  // bit 4\r
+    UINT32    Reserved                  : 27; // Reserved bit 5:31\r
   } Bits;\r
-  UINT32   Uint32;\r
+  UINT32    Uint32;\r
 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r
 \r
 typedef union {\r
   struct {\r
-    UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r
-    UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7\r
+    UINT8    DownstreamPortTransmitterPreset : 4; // bit 0..3\r
+    UINT8    UpstreamPortTransmitterPreset   : 4; // bit 4..7\r
   } Bits;\r
-  UINT8   Uint8;\r
+  UINT8    Uint8;\r
 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r
 \r
 typedef struct {\r
-  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;\r
-  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES              Capablities;\r
-  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL                   Control;\r
-  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS                    Status;\r
-  UINT32                                                        LocalDataParityMismatchStatus;\r
-  UINT32                                                        FirstRetimerDataParityMismatchStatus;\r
-  UINT32                                                        SecondRetimerDataParityMismatchStatus;\r
-  UINT32                                                        Reserved;\r
-  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                         Header;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES                 Capablities;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL                      Control;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS                       Status;\r
+  UINT32                                                           LocalDataParityMismatchStatus;\r
+  UINT32                                                           FirstRetimerDataParityMismatchStatus;\r
+  UINT32                                                           SecondRetimerDataParityMismatchStatus;\r
+  UINT32                                                           Reserved;\r
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL    LaneEqualizationControl[1];\r
 } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r
 ///@}\r
 \r
@@ -84,26 +84,26 @@ typedef struct {
 ///@{\r
 typedef union {\r
   struct {\r
-    UINT32 DvsecVendorId                                        : 16; //bit 0..15\r
-    UINT32 DvsecRevision                                        : 4;  //bit 16..19\r
-    UINT32 DvsecLength                                          : 12; //bit 20..31\r
-  }Bits;\r
-  UINT32                                                        Uint32;\r
-}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\r
+    UINT32    DvsecVendorId : 16;                                     // bit 0..15\r
+    UINT32    DvsecRevision : 4;                                      // bit 16..19\r
+    UINT32    DvsecLength   : 12;                                     // bit 20..31\r
+  } Bits;\r
+  UINT32    Uint32;\r
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\r
 \r
 typedef union {\r
   struct {\r
-    UINT16 DvsecId                                              : 16; //bit 0..15\r
-  }Bits;\r
-  UINT16                                                        Uint16;\r
-}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\r
+    UINT16    DvsecId : 16;                                           // bit 0..15\r
+  } Bits;\r
+  UINT16    Uint16;\r
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\r
 \r
 typedef struct {\r
-  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;\r
-  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1               DesignatedVendorSpecificHeader1;\r
-  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2               DesignatedVendorSpecificHeader2;\r
-  UINT8                                                         DesignatedVendorSpecific[1];\r
-}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\r
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER           Header;\r
+  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1    DesignatedVendorSpecificHeader1;\r
+  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2    DesignatedVendorSpecificHeader2;\r
+  UINT8                                              DesignatedVendorSpecific[1];\r
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\r
 ///@}\r
 \r
 #pragma pack()\r