Main SAL API's defined in Intel Itanium Processor Family System Abstraction\r
Layer Specification Revision 3.2 (December 2003)\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved<BR>\r
+This program and the accompanying materials are licensed and made available under \r
+the terms and conditions of the BSD License that accompanies this distribution. \r
+The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php. \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
**/\r
\r
///\r
#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
///\r
-/// Call completed without error but some information was lost due to overflow. \r
+/// Call completed without error, but some information was lost due to overflow. \r
///\r
#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)\r
///\r
#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
\r
///\r
-/// Return registers from SAL\r
+/// Return registers from SAL.\r
///\r
typedef struct {\r
///\r
- /// SAL return status value in r8\r
+ /// SAL return status value in r8.\r
///\r
EFI_SAL_STATUS Status;\r
///\r
- /// SAL returned value in r9\r
+ /// SAL returned value in r9.\r
///\r
UINTN r9;\r
///\r
- /// SAL returned value in r10\r
+ /// SAL returned value in r10.\r
///\r
UINTN r10;\r
///\r
- /// SAL returned value in r11\r
+ /// SAL returned value in r11.\r
///\r
UINTN r11;\r
} SAL_RETURN_REGS;\r
0x04XXXXXX to 0xFFFFFFFF - Reserved.\r
@param Arg1 The first parameter of the architected/OEM specific SAL functions.\r
@param Arg2 The second parameter of the architected/OEM specific SAL functions.\r
- @param Arg3 The third parameter passed to the ESAL function based\r
- @param Arg4 The fourth parameter passed to the ESAL function based\r
- @param Arg5 The fifth parameter passed to the ESAL function based\r
- @param Arg6 The sixth parameter passed to the ESAL function\r
- @param Arg7 The seventh parameter passed to the ESAL function based\r
+ @param Arg3 The third parameter passed to the ESAL function based.\r
+ @param Arg4 The fourth parameter passed to the ESAL function based.\r
+ @param Arg5 The fifth parameter passed to the ESAL function based.\r
+ @param Arg6 The sixth parameter passed to the ESAL function.\r
+ @param Arg7 The seventh parameter passed to the ESAL function based.\r
\r
@return r8 Return status: positive number indicates successful,\r
negative number indicates failure.\r
#define EFI_SAL_SET_INIT_VECTOR 0x1\r
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
///\r
-/// Format of length_cs_n argument.\r
+/// The format of a length_cs_n argument.\r
///\r
typedef struct {\r
UINT64 Length : 32;\r
#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0\r
#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1\r
///\r
-/// Format of PCI Compatible Address\r
+/// The format of PCI Compatible Address.\r
///\r
typedef struct {\r
UINT64 Register : 8;\r
UINT64 Reserved : 32;\r
} SAL_PCI_ADDRESS;\r
///\r
-/// Format of Extended Register Address\r
+/// The format of Extended Register Address.\r
///\r
typedef struct {\r
UINT64 Register : 8;\r
UINT8 Reserved2[40];\r
} SAL_UPDATE_PAL_DATA_BLOCK;\r
///\r
-/// Data structure pointed by parameter param_buf.\r
+/// Data structure pointed by the parameter param_buf.\r
/// It is a 16-byte aligned data structure in memory with a length of 32 bytes\r
/// that describes the new firmware. This information is organized in the form\r
/// of a linked list with each element describing one firmware component.\r
} SAL_UPDATE_PAL_INFO_BLOCK;\r
\r
///\r
-/// SAL System Table Definitions\r
+/// SAL System Table Definitions.\r
///\r
#pragma pack(1)\r
typedef struct {\r
///\r
- /// The ASCII string representation of "SST_" which confirms the presence of the table. \r
+ /// The ASCII string representation of "SST_" that confirms the presence of the table. \r
/// \r
UINT32 Signature;\r
///\r
UINT32 Length;\r
///\r
/// The revision number of the Itanium Processor Family System Abstraction Layer\r
- /// Specification supported by the SAL implementation in binary coded decimal (BCD) format.\r
+ /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.\r
///\r
UINT16 SalRevision;\r
///\r
#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
\r
///\r
-/// Format of Entrypoint Descriptor Entry\r
+/// Format of Entrypoint Descriptor Entry.\r
///\r
typedef struct {\r
- UINT8 Type; ///< Type here should be 0\r
+ UINT8 Type; ///< Type here should be 0.\r
UINT8 Reserved[7];\r
UINT64 PalProcEntry;\r
UINT64 SalProcEntry;\r
} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
\r
///\r
-/// Format of Platform Features Descriptor Entry\r
+/// Format of Platform Features Descriptor Entry.\r
///\r
typedef struct {\r
- UINT8 Type; ///< Type here should be 2\r
+ UINT8 Type; ///< Type here should be 2.\r
UINT8 PlatformFeatures;\r
UINT8 Reserved[14];\r
} SAL_ST_PLATFORM_FEATURES;\r
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
\r
///\r
-/// Format of Translation Register Descriptor Entry\r
+/// Format of Translation Register Descriptor Entry.\r
///\r
typedef struct {\r
- UINT8 Type; ///< Type here should be 3\r
+ UINT8 Type; ///< Type here should be 3.\r
UINT8 TRType;\r
UINT8 TRNumber;\r
UINT8 Reserved[5];\r
#define EFI_SAL_ST_TR_USAGE_DATA 01\r
\r
///\r
-/// Definition of Coherence Domain Information\r
+/// Definition of Coherence Domain Information.\r
///\r
typedef struct {\r
UINT64 NumberOfProcessors;\r
} SAL_COHERENCE_DOMAIN_INFO;\r
\r
///\r
-/// Format of Purge Translation Cache Coherence Domain Entry\r
+/// Format of Purge Translation Cache Coherence Domain Entry.\r
///\r
typedef struct {\r
- UINT8 Type; ///< Type here should be 4\r
+ UINT8 Type; ///< Type here should be 4.\r
UINT8 Reserved[3];\r
UINT32 NumberOfDomains;\r
SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
\r
///\r
-/// Format of Application Processor Wake-Up Descriptor Entry\r
+/// Format of Application Processor Wake-Up Descriptor Entry.\r
///\r
typedef struct {\r
- UINT8 Type; ///< Type here should be 5\r
+ UINT8 Type; ///< Type here should be 5.\r
UINT8 WakeUpType;\r
UINT8 Reserved[6];\r
UINT64 ExternalInterruptVector;\r
} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
\r
///\r
-/// Format of Firmware Interface Table (FIT) Entry\r
+/// Format of Firmware Interface Table (FIT) Entry.\r
///\r
typedef struct {\r
UINT64 Address;\r
//\r
\r
///\r
-/// Format of TimeStamp field in Record Header\r
+/// Format of TimeStamp field in Record Header.\r
///\r
typedef struct {\r
UINT8 Seconds;\r
UINT8 Century;\r
} SAL_TIME_STAMP;\r
///\r
-/// Definition of Record Header\r
+/// Definition of Record Header.\r
///\r
typedef struct {\r
UINT64 RecordId;\r
UINT8 OemPlatformId[16];\r
} SAL_RECORD_HEADER;\r
///\r
-/// Definition of Section Header\r
+/// Definition of Section Header.\r
///\r
typedef struct {\r
GUID Guid;\r
} SAL_SEC_HEADER;\r
\r
///\r
-/// GUID of Processor Machine Check Errors\r
+/// GUID of Processor Machine Check Errors.\r
///\r
#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
{ \\r
#define TARGER_ID_VALID_BIT_MASK 0x8\r
#define PRECISE_IP_VALID_BIT_MASK 0x10\r
///\r
-/// Definition of MOD_ERROR_INFO_STRUCT\r
+/// Definition of MOD_ERROR_INFO_STRUCT.\r
///\r
typedef struct {\r
UINT64 InfoValid : 1;\r
UINT64 Ip;\r
} MOD_ERROR_INFO;\r
///\r
-/// Definition of CPUID_INFO_STRUCT\r
+/// Definition of CPUID_INFO_STRUCT.\r
///\r
typedef struct {\r
UINT8 CpuidInfo[40];\r
#define RR_VALID_BIT_MASK 0x10\r
#define FR_VALID_BIT_MASK 0x20\r
///\r
-/// Definition of PSI_STATIC_STRUCT\r
+/// Definition of PSI_STATIC_STRUCT.\r
///\r
typedef struct {\r
UINT64 ValidFieldBits;\r
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
///\r
-/// Definition of Processor Machine Check Error Record\r
+/// Definition of Processor Machine Check Error Record.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_PROCESSOR_ERROR_RECORD;\r
\r
///\r
-/// GUID of Platform Memory Device Error Info\r
+/// GUID of Platform Memory Device Error Info.\r
///\r
#define SAL_MEMORY_ERROR_RECORD_INFO \\r
{ \\r
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
///\r
-/// Definition of Platform Memory Device Error Info Record\r
+/// Definition of Platform Memory Device Error Info Record.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_MEMORY_ERROR_RECORD;\r
\r
///\r
-/// GUID of Platform PCI Bus Error Info\r
+/// GUID of Platform PCI Bus Error Info.\r
///\r
#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
{ \\r
#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
\r
///\r
-/// Designated PCI Bus identifier\r
+/// Designated PCI Bus identifier.\r
///\r
typedef struct {\r
UINT8 BusNumber;\r
} PCI_BUS_ID;\r
\r
///\r
-/// Definition of Platform PCI Bus Error Info Record\r
+/// Definition of Platform PCI Bus Error Info Record.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_PCI_BUS_ERROR_RECORD;\r
\r
///\r
-/// GUID of Platform PCI Component Error Info\r
+/// GUID of Platform PCI Component Error Info.\r
///\r
#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
{ \\r
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
///\r
-/// Format of PCI Component Information to identify the device\r
+/// Format of PCI Component Information to identify the device.\r
///\r
typedef struct {\r
UINT16 VendorId;\r
UINT8 Reserved[5];\r
} PCI_COMP_INFO;\r
///\r
-/// Definition of Platform PCI Component Error Info\r
+/// Definition of Platform PCI Component Error Info.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_PCI_COMPONENT_ERROR_RECORD;\r
\r
///\r
-/// Platform SEL Device Error Info\r
+/// Platform SEL Device Error Info.\r
///\r
#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \\r
{ \\r
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
///\r
-/// Definition of Platform SEL Device Error Info Record\r
+/// Definition of Platform SEL Device Error Info Record.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_SEL_DEVICE_ERROR_RECORD;\r
\r
///\r
-/// GUID of Platform SMBIOS Device Error Info\r
+/// GUID of Platform SMBIOS Device Error Info.\r
///\r
#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
{ \\r
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
///\r
-/// Definition of Platform SMBIOS Device Error Info Record\r
+/// Definition of Platform SMBIOS Device Error Info Record.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
\r
///\r
-/// GUID of Platform Specific Error Info\r
+/// GUID of Platform Specific Error Info.\r
///\r
#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
{ \\r
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
///\r
-/// Definition of Platform Specific Error Info Record\r
+/// Definition of Platform Specific Error Info Record.\r
///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
\r
///\r
-/// Union of all the possible SAL Error Record Types\r
+/// Union of all the possible SAL Error Record Types.\r
///\r
typedef union {\r
SAL_RECORD_HEADER *RecordHeader;\r
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