/** @file\r
- Main SAL API's defined in SAL 3.0 specification. \r
+ Main SAL API's defined in Intel Itanium Processor Family System Abstraction\r
+ Layer Specification Revision 3.2 (December 2003)\r
\r
- Copyright (c) 2006, Intel Corporation \r
+ Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
#ifndef __SAL_API_H__\r
#define __SAL_API_H__\r
\r
-//\r
-// FIT Types \r
-// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
-//\r
-#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
-#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
-//\r
-// type from 0x02 to 0x0E is reserved.\r
-//\r
-#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
-//\r
-// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
-//\r
-#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
-#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
-\r
-//\r
-// EFI_SAL_STATUS \r
-//\r
+///\r
+/// SAL return status type \r
+///\r
typedef UINTN EFI_SAL_STATUS;\r
\r
+///\r
+/// Call completed without error. \r
+///\r
#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
+///\r
+/// Call completed without error but some information was lost due to overflow. \r
+///\r
+#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)\r
+///\r
+/// Call completed without error; effect a warm boot of the system to complete the update.\r
+///\r
+#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)\r
+///\r
+/// More information is available for retrieval. \r
+///\r
#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
+///\r
+/// Not implemented.\r
+///\r
#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
+///\r
+/// Invalid Argument.\r
+///\r
#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
+///\r
+/// Call completed without error. \r
+///\r
#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
+///\r
+/// Virtual address not registered. \r
+///\r
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
+///\r
+/// No information available. \r
+///\r
#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
+///\r
+/// Scratch buffer required.\r
+///\r
#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
\r
-//\r
-// Return values from SAL\r
-//\r
+///\r
+/// Return registers from SAL\r
+///\r
typedef struct {\r
- EFI_SAL_STATUS Status; // register r8\r
+ ///\r
+ /// SAL return status value in r8\r
+ ///\r
+ EFI_SAL_STATUS Status;\r
+ ///\r
+ /// SAL returned value in r9\r
+ ///\r
UINTN r9;\r
+ ///\r
+ /// SAL returned value in r10\r
+ ///\r
UINTN r10;\r
+ ///\r
+ /// SAL returned value in r11\r
+ ///\r
UINTN r11;\r
} SAL_RETURN_REGS;\r
\r
-//\r
-// Delivery Mode of IPF CPU.\r
-//\r
-typedef enum {\r
- EFI_DELIVERY_MODE_INT,\r
- EFI_DELIVERY_MODE_MPreserved1,\r
- EFI_DELIVERY_MODE_PMI,\r
- EFI_DELIVERY_MODE_MPreserved2,\r
- EFI_DELIVERY_MODE_NMI,\r
- EFI_DELIVERY_MODE_INIT,\r
- EFI_DELIVERY_MODE_MPreserved3,\r
- EFI_DELIVERY_MODE_ExtINT\r
-} EFI_DELIVERY_MODE;\r
-\r
-typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
- (\r
- IN UINT64 FunctionId,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4,\r
- IN UINT64 Arg5,\r
- IN UINT64 Arg6,\r
- IN UINT64 Arg7,\r
- IN UINT64 Arg8\r
+/**\r
+ Prototype of SAL procedures.\r
+\r
+ @param FunctionId Functional identifier.\r
+ The upper 32 bits are ignored and only the lower 32 bits\r
+ are used. The following functional identifiers are defined:\r
+ 0x01XXXXXX - Architected SAL functional group.\r
+ 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is\r
+ allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.\r
+ 0x04XXXXXX to 0xFFFFFFFF - Reserved.\r
+ @param Arg1 The first parameter of the architected/OEM specific SAL functions.\r
+ @param Arg2 The second parameter of the architected/OEM specific SAL functions.\r
+ @param Arg3 The third parameter passed to the ESAL function based\r
+ @param Arg4 The fourth parameter passed to the ESAL function based\r
+ @param Arg5 The fifth parameter passed to the ESAL function based\r
+ @param Arg6 The sixth parameter passed to the ESAL function\r
+ @param Arg7 The seventh parameter passed to the ESAL function based\r
+\r
+ @return r8 Return status: positive number indicates successful,\r
+ negative number indicates failure.\r
+ r9 Other return parameter in r9.\r
+ r10 Other return parameter in r10.\r
+ r11 Other return parameter in r11.\r
+\r
+**/\r
+typedef\r
+SAL_RETURN_REGS\r
+(EFIAPI *SAL_PROC) (\r
+ IN UINT64 FunctionId,\r
+ IN UINT64 Arg1,\r
+ IN UINT64 Arg2,\r
+ IN UINT64 Arg3,\r
+ IN UINT64 Arg4,\r
+ IN UINT64 Arg5,\r
+ IN UINT64 Arg6,\r
+ IN UINT64 Arg7\r
);\r
\r
//\r
// SAL Procedure FunctionId definition\r
//\r
+\r
+///\r
+/// Register software code locations with SAL.\r
+///\r
#define EFI_SAL_SET_VECTORS 0x01000000\r
+///\r
+/// Return Machine State information obtained by SAL.\r
+///\r
#define EFI_SAL_GET_STATE_INFO 0x01000001\r
+///\r
+/// Obtain size of Machine State information.\r
+///\r
#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
+///\r
+/// Clear Machine State information.\r
+///\r
#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
+///\r
+/// Cause the processor to go into a spin loop within SAL.\r
+///\r
#define EFI_SAL_MC_RENDEZ 0x01000004\r
+///\r
+/// Register the machine check interface layer with SAL.\r
+///\r
#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
+///\r
+/// Register the physical addresses of locations needed by SAL.\r
+///\r
#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
+///\r
+/// Flush the instruction or data caches.\r
+///\r
#define EFI_SAL_CACHE_FLUSH 0x01000008\r
+///\r
+/// Initialize the instruction and data caches.\r
+///\r
#define EFI_SAL_CACHE_INIT 0x01000009\r
+///\r
+/// Read from the PCI configuration space.\r
+///\r
#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
+///\r
+/// Write to the PCI configuration space.\r
+///\r
#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
+///\r
+/// Return the base frequency of the platform.\r
+///\r
#define EFI_SAL_FREQ_BASE 0x01000012\r
+///\r
+/// Returns information on the physical processor mapping within the platform.\r
+///\r
#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
+///\r
+/// Update the contents of firmware blocks.\r
+///\r
#define EFI_SAL_UPDATE_PAL 0x01000020\r
\r
#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
// Not much point in using typedefs or enums because all params\r
// are UINT64 and the entry point is common\r
//\r
-// EFI_SAL_SET_VECTORS\r
+\r
+//\r
+// Parameter of EFI_SAL_SET_VECTORS\r
+//\r
+// Vector type\r
//\r
#define EFI_SAL_SET_MCA_VECTOR 0x0\r
#define EFI_SAL_SET_INIT_VECTOR 0x1\r
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
-\r
+///\r
+/// Format of length_cs_n argument.\r
+///\r
typedef struct {\r
UINT64 Length : 32;\r
UINT64 ChecksumValid : 1;\r
} SAL_SET_VECTORS_CS_N;\r
\r
//\r
-// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
-// EFI_SAL_CLEAR_STATE_INFO\r
+// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO\r
+// \r
+// Type of information\r
//\r
#define EFI_SAL_MCA_STATE_INFO 0x0\r
#define EFI_SAL_INIT_STATE_INFO 0x1\r
#define EFI_SAL_CP_STATE_INFO 0x3\r
\r
//\r
-// EFI_SAL_MC_SET_PARAMS\r
+// Parameter of EFI_SAL_MC_SET_PARAMS\r
+//\r
+// Unsigned 64-bit integer value for the parameter type of the machine check interface\r
//\r
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
-\r
+//\r
+// Unsigned 64-bit integer value indicating whether interrupt vector or\r
+// memory address is specified\r
+//\r
#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
\r
//\r
-// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
+// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
+//\r
+// The encoded value of the entity whose physical address is registered\r
//\r
#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
\r
//\r
-// EFI_SAL_CACHE_FLUSH\r
+// Parameter of EFI_SAL_CACHE_FLUSH\r
+//\r
+// Unsigned 64-bit integer denoting type of cache flush operation\r
//\r
#define EFI_SAL_FLUSH_I_CACHE 0x01\r
#define EFI_SAL_FLUSH_D_CACHE 0x02\r
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
\r
//\r
-// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
+// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE\r
+//\r
+// PCI config size\r
//\r
#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
-\r
+//\r
+// The type of PCI configuration address\r
+//\r
+#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0\r
+#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1\r
+///\r
+/// Format of PCI Compatible Address\r
+///\r
typedef struct {\r
UINT64 Register : 8;\r
UINT64 Function : 3;\r
UINT64 Segment : 8;\r
UINT64 Reserved : 32;\r
} SAL_PCI_ADDRESS;\r
+///\r
+/// Format of Extended Register Address\r
+///\r
+typedef struct {\r
+ UINT64 Register : 8;\r
+ UINT64 ExtendedRegister : 4;\r
+ UINT64 Function : 3;\r
+ UINT64 Device : 5;\r
+ UINT64 Bus : 8;\r
+ UINT64 Segment : 16;\r
+ UINT64 Reserved : 20;\r
+} SAL_PCI_EXTENDED_REGISTER_ADDRESS;\r
\r
//\r
-// EFI_SAL_FREQ_BASE\r
+// Parameter of EFI_SAL_FREQ_BASE\r
+//\r
+// Unsigned 64-bit integer specifying the type of clock source\r
//\r
#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
\r
//\r
-// EFI_SAL_UPDATE_PAL\r
+// Parameter and return value of EFI_SAL_UPDATE_PAL\r
+//\r
+// Return parameter provides additional information on the\r
+// failure when the status field contains a value of -3,\r
+// returned in r9.\r
//\r
#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
-\r
+///\r
+/// 64-byte header of update data block.\r
+///\r
typedef struct {\r
UINT32 Size;\r
UINT32 MmddyyyyDate;\r
UINT8 Reserved[5];\r
UINT64 FwVendorId;\r
} SAL_UPDATE_PAL_DATA_BLOCK;\r
-\r
+///\r
+/// Data structure pointed by parameter param_buf.\r
+/// It is a 16-byte aligned data structure in memory with a length of 32 bytes\r
+/// that describes the new firmware. This information is organized in the form\r
+/// of a linked list with each element describing one firmware component.\r
+///\r
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
UINT8 Reserved[15];\r
} SAL_UPDATE_PAL_INFO_BLOCK;\r
\r
-//\r
-// SAL System Table Definitions\r
-//\r
+///\r
+/// SAL System Table Definitions\r
+///\r
#pragma pack(1)\r
typedef struct {\r
+ ///\r
+ /// The ASCII string representation of "SST_" which confirms the presence of the table. \r
+ /// \r
UINT32 Signature;\r
+ ///\r
+ /// The length of the entire table in bytes, starting from offset zero and including the\r
+ /// header and all entries indicated by the EntryCount field.\r
+ ///\r
UINT32 Length;\r
+ ///\r
+ /// The revision number of the Itanium Processor Family System Abstraction Layer\r
+ /// Specification supported by the SAL implementation in binary coded decimal (BCD) format.\r
+ ///\r
UINT16 SalRevision;\r
+ ///\r
+ /// The number of entries in the variable portion of the table.\r
+ ///\r
UINT16 EntryCount;\r
+ ///\r
+ /// A modulo checksum of the entire table and the entries following this table.\r
+ ///\r
UINT8 CheckSum;\r
+ ///\r
+ /// Unused, must be zero.\r
+ ///\r
UINT8 Reserved[7];\r
+ ///\r
+ /// Version Number of the SAL_A firmware implementation in BCD format.\r
+ ///\r
UINT16 SalAVersion;\r
+ ///\r
+ /// Version Number of the SAL_B firmware implementation in BCD format.\r
+ ///\r
UINT16 SalBVersion;\r
+ ///\r
+ /// An ASCII identification string which uniquely identifies the manufacturer\r
+ /// of the system hardware.\r
+ ///\r
UINT8 OemId[32];\r
+ ///\r
+ /// An ASCII identification string which uniquely identifies a family of\r
+ /// compatible products from the manufacturer.\r
+ ///\r
UINT8 ProductId[32];\r
+ ///\r
+ /// Unused, must be zero.\r
+ ///\r
UINT8 Reserved2[8];\r
} SAL_SYSTEM_TABLE_HEADER;\r
-#pragma pack()\r
\r
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
-#define EFI_SAL_REVISION 0x0300\r
+#define EFI_SAL_REVISION 0x0320\r
//\r
// SAL System Types\r
//\r
#define EFI_SAL_ST_PTC_SIZE 16\r
#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
\r
-#pragma pack(1)\r
+///\r
+/// Format of Entrypoint Descriptor Entry\r
+///\r
typedef struct {\r
- UINT8 Type; // Type == 0\r
+ UINT8 Type; ///< Type here should be 0\r
UINT8 Reserved[7];\r
UINT64 PalProcEntry;\r
UINT64 SalProcEntry;\r
UINT64 Reserved2[2];\r
} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
\r
-#pragma pack(1)\r
+///\r
+/// Format of Platform Features Descriptor Entry\r
+///\r
typedef struct {\r
- UINT8 Type; // Type == 2\r
+ UINT8 Type; ///< Type here should be 2\r
UINT8 PlatformFeatures;\r
UINT8 Reserved[14];\r
} SAL_ST_PLATFORM_FEATURES;\r
-#pragma pack()\r
\r
+//\r
+// Value of Platform Feature List\r
+//\r
#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
\r
-#pragma pack(1)\r
+///\r
+/// Format of Translation Register Descriptor Entry\r
+///\r
typedef struct {\r
- UINT8 Type; // Type == 3\r
+ UINT8 Type; ///< Type here should be 3\r
UINT8 TRType;\r
UINT8 TRNumber;\r
UINT8 Reserved[5];\r
UINT64 EncodedPageSize;\r
UINT64 Reserved1;\r
} SAL_ST_TR_DECRIPTOR;\r
-#pragma pack()\r
\r
+//\r
+// Type of Translation Register\r
+//\r
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
#define EFI_SAL_ST_TR_USAGE_DATA 01\r
\r
-#pragma pack(1)\r
+///\r
+/// Definition of Coherence Domain Information\r
+///\r
typedef struct {\r
UINT64 NumberOfProcessors;\r
UINT64 LocalIDRegister;\r
} SAL_COHERENCE_DOMAIN_INFO;\r
-#pragma pack()\r
-\r
-#pragma pack(1)\r
+ \r
+///\r
+/// Format of Purge Translation Cache Coherence Domain Entry\r
+///\r
typedef struct {\r
- UINT8 Type; // Type == 4\r
+ UINT8 Type; ///< Type here should be 4\r
UINT8 Reserved[3];\r
UINT32 NumberOfDomains;\r
SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
-#pragma pack()\r
\r
-#pragma pack(1)\r
+///\r
+/// Format of Application Processor Wake-Up Descriptor Entry\r
+///\r
typedef struct {\r
- UINT8 Type; // Type == 5\r
+ UINT8 Type; ///< Type here should be 5\r
UINT8 WakeUpType;\r
UINT8 Reserved[6];\r
UINT64 ExternalInterruptVector;\r
} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
-#pragma pack()\r
-//\r
-// FIT Entry\r
-//\r
-#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
-#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
-#define EFI_SAL_FIT_PALB_TYPE 01\r
\r
+///\r
+/// Format of Firmware Interface Table (FIT) Entry\r
+///\r
typedef struct {\r
UINT64 Address;\r
UINT8 Size[3];\r
UINT8 CheckSumValid : 1;\r
UINT8 CheckSum;\r
} EFI_SAL_FIT_ENTRY;\r
+//\r
+// FIT Types \r
+//\r
+#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
+#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
+//\r
+// Type from 0x02 to 0x0D is reserved.\r
+//\r
+#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E\r
+#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
+//\r
+// OEM-defined type range is from 0x10 to 0x7E.\r
+// Here we defined the PEI_CORE type as 0x10\r
+//\r
+#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
+#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
\r
//\r
-// SAL Common Record Header\r
+// FIT Entry\r
//\r
-typedef struct {\r
- UINT16 Length;\r
- UINT8 Data[1024];\r
-} SAL_OEM_DATA;\r
+#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
+#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
+#define EFI_SAL_FIT_PALB_TYPE 01\r
\r
+//\r
+// Following definitions are for Error Record Structure\r
+//\r
+\r
+///\r
+/// Format of TimeStamp field in Record Header\r
+///\r
typedef struct {\r
UINT8 Seconds;\r
UINT8 Minutes;\r
UINT8 Year;\r
UINT8 Century;\r
} SAL_TIME_STAMP;\r
-\r
+///\r
+/// Definition of Record Header\r
+///\r
typedef struct {\r
UINT64 RecordId;\r
UINT16 Revision;\r
SAL_TIME_STAMP TimeStamp;\r
UINT8 OemPlatformId[16];\r
} SAL_RECORD_HEADER;\r
-\r
+///\r
+/// Definition of Section Header\r
+///\r
typedef struct {\r
- GUID Guid;\r
+ GUID Guid;\r
UINT16 Revision;\r
UINT8 ErrorRecoveryInfo;\r
UINT8 Reserved;\r
UINT32 SectionLength;\r
} SAL_SEC_HEADER;\r
\r
-//\r
-// SAL Processor Record\r
-//\r
+///\r
+/// GUID of Processor Machine Check Errors\r
+///\r
#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for valid bits of MOD_ERROR_INFO\r
+//\r
#define CHECK_INFO_VALID_BIT_MASK 0x1\r
#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
#define TARGER_ID_VALID_BIT_MASK 0x8\r
#define PRECISE_IP_VALID_BIT_MASK 0x10\r
-\r
+///\r
+/// Definition of MOD_ERROR_INFO_STRUCT\r
+///\r
typedef struct {\r
UINT64 InfoValid : 1;\r
UINT64 ReqValid : 1;\r
UINT64 Target;\r
UINT64 Ip;\r
} MOD_ERROR_INFO;\r
-\r
+///\r
+/// Definition of CPUID_INFO_STRUCT\r
+///\r
typedef struct {\r
UINT8 CpuidInfo[40];\r
UINT8 Reserved;\r
UINT64 FrLow;\r
UINT64 FrHigh;\r
} FR_STRUCT;\r
-\r
+//\r
+// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits\r
+//\r
#define MIN_STATE_VALID_BIT_MASK 0x1\r
#define BR_VALID_BIT_MASK 0x2\r
#define CR_VALID_BIT_MASK 0x4\r
#define AR_VALID_BIT_MASK 0x8\r
#define RR_VALID_BIT_MASK 0x10\r
#define FR_VALID_BIT_MASK 0x20\r
-\r
+///\r
+/// Definition of PSI_STATIC_STRUCT\r
+///\r
typedef struct {\r
UINT64 ValidFieldBits;\r
UINT8 MinStateInfo[1024];\r
UINT64 Rr[8];\r
FR_STRUCT Fr[128];\r
} PSI_STATIC_STRUCT;\r
-\r
+//\r
+// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits\r
+//\r
#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
-\r
+///\r
+/// Definition of Processor Machine Check Error Record\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
PSI_STATIC_STRUCT PsiValidData;\r
} SAL_PROCESSOR_ERROR_RECORD;\r
\r
-//\r
-// Sal Platform memory Error Record\r
-//\r
+///\r
+/// GUID of Platform Memory Device Error Info\r
+///\r
#define SAL_MEMORY_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits\r
+//\r
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
#define MEMORY_ADDR_BIT_MASK 0x4\r
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
-\r
+///\r
+/// Definition of Platform Memory Device Error Info Record\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
UINT8 MemPlatformOemId[16];\r
} SAL_MEMORY_ERROR_RECORD;\r
\r
-//\r
-// PCI BUS Errors\r
-//\r
+///\r
+/// GUID of Platform PCI Bus Error Info\r
+///\r
#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits\r
+//\r
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
UINT8 BusNumber;\r
UINT8 SegmentNumber;\r
} PCI_BUS_ID;\r
-\r
+///\r
+/// Definition of Platform PCI Bus Error Info Record\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
UINT8 PciBusOemId[16];\r
} SAL_PCI_BUS_ERROR_RECORD;\r
\r
-//\r
-// PCI Component Errors\r
-//\r
+///\r
+/// GUID of Platform PCI Component Error Info\r
+///\r
#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits\r
+//\r
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
-\r
+///\r
+/// Format of PCI Component Information to identify the device\r
+///\r
typedef struct {\r
UINT16 VendorId;\r
UINT16 DeviceId;\r
UINT8 SegmentNumber;\r
UINT8 Reserved[5];\r
} PCI_COMP_INFO;\r
-\r
+///\r
+/// Definition of Platform PCI Component Error Info\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
UINT8 PciBusOemId[16];\r
} SAL_PCI_COMPONENT_ERROR_RECORD;\r
\r
-//\r
-// Sal Device Errors Info.\r
-//\r
-#define SAL_DEVICE_ERROR_RECORD_INFO \\r
+///\r
+/// Platform SEL Device Error Info\r
+///\r
+#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits\r
+//\r
#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
-\r
+///\r
+/// Definition of Platform SEL Device Error Info Record\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
UINT8 Data1;\r
UINT8 Data2;\r
UINT8 Data3;\r
-} SAL_DEVICE_ERROR_RECORD;\r
+} SAL_SEL_DEVICE_ERROR_RECORD;\r
\r
-//\r
-// Sal SMBIOS Device Errors Info.\r
-//\r
+///\r
+/// GUID of Platform SMBIOS Device Error Info\r
+///\r
#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits\r
+//\r
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
-\r
+///\r
+/// Definition of Platform SMBIOS Device Error Info Record\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
UINT8 SmbiosBcdTimeStamp[6];\r
} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
\r
-//\r
-// Sal Platform Specific Errors Info.\r
-//\r
+///\r
+/// GUID of Platform Specific Error Info\r
+///\r
#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
{ \\r
0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
-\r
+//\r
+// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits\r
+//\r
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
-\r
+///\r
+/// Definition of Platform Specific Error Info Record\r
+///\r
typedef struct {\r
SAL_SEC_HEADER SectionHeader;\r
UINT64 ValidationBits;\r
UINT8 OemComponentId[16];\r
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
\r
-//\r
-// Union of all the possible Sal Record Types\r
-//\r
+///\r
+/// Union of all the possible SAL Error Record Types\r
+///\r
typedef union {\r
SAL_RECORD_HEADER *RecordHeader;\r
SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
- SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
+ SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord;\r
SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
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