MdePkg: Apply uncrustify changes

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / SdramSpd.h

diff --git a/MdePkg/Include/IndustryStandard/SdramSpd.h b/MdePkg/Include/IndustryStandard/SdramSpd.h
index 82aca249d376f5328c495c6e3e17fae2d4633d3f..2eb4d9e7cd7291efa7c0f07850bfa17a35713f1e 100644 (file)
--- a/MdePkg/Include/IndustryStandard/SdramSpd.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -15,50 +15,50 @@
 //\r
 // SDRAM SPD field definitions\r
 //\r
-#define SPD_MEMORY_TYPE                 2\r
-#define SPD_SDRAM_ROW_ADDR              3\r
-#define SPD_SDRAM_COL_ADDR              4\r
-#define SPD_SDRAM_MODULE_ROWS           5\r
-#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6\r
-#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7\r
-#define SPD_SDRAM_ECC_SUPPORT           11\r
-#define SPD_SDRAM_REFRESH               12\r
-#define SPD_SDRAM_WIDTH                 13\r
-#define SPD_SDRAM_ERROR_WIDTH           14\r
-#define SPD_SDRAM_BURST_LENGTH          16\r
-#define SPD_SDRAM_NO_OF_BANKS           17\r
-#define SPD_SDRAM_CAS_LATENCY           18\r
-#define SPD_SDRAM_MODULE_ATTR           21\r
+#define SPD_MEMORY_TYPE                  2\r
+#define SPD_SDRAM_ROW_ADDR               3\r
+#define SPD_SDRAM_COL_ADDR               4\r
+#define SPD_SDRAM_MODULE_ROWS            5\r
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB  6\r
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB  7\r
+#define SPD_SDRAM_ECC_SUPPORT            11\r
+#define SPD_SDRAM_REFRESH                12\r
+#define SPD_SDRAM_WIDTH                  13\r
+#define SPD_SDRAM_ERROR_WIDTH            14\r
+#define SPD_SDRAM_BURST_LENGTH           16\r
+#define SPD_SDRAM_NO_OF_BANKS            17\r
+#define SPD_SDRAM_CAS_LATENCY            18\r
+#define SPD_SDRAM_MODULE_ATTR            21\r
 \r
-#define SPD_SDRAM_TCLK1_PULSE           9   ///< cycle time for highest cas latency\r
-#define SPD_SDRAM_TAC1_PULSE            10  ///< access time for highest cas latency\r
-#define SPD_SDRAM_TCLK2_PULSE           23  ///< cycle time for 2nd highest cas latency\r
-#define SPD_SDRAM_TAC2_PULSE            24  ///< access time for 2nd highest cas latency\r
-#define SPD_SDRAM_TCLK3_PULSE           25  ///< cycle time for 3rd highest cas latency\r
-#define SPD_SDRAM_TAC3_PULSE            26  ///< access time for 3rd highest cas latency\r
-#define SPD_SDRAM_MIN_PRECHARGE         27\r
-#define SPD_SDRAM_ACTIVE_MIN            28\r
-#define SPD_SDRAM_RAS_CAS               29\r
-#define SPD_SDRAM_RAS_PULSE             30\r
-#define SPD_SDRAM_DENSITY               31\r
+#define SPD_SDRAM_TCLK1_PULSE    9          ///< cycle time for highest cas latency\r
+#define SPD_SDRAM_TAC1_PULSE     10         ///< access time for highest cas latency\r
+#define SPD_SDRAM_TCLK2_PULSE    23         ///< cycle time for 2nd highest cas latency\r
+#define SPD_SDRAM_TAC2_PULSE     24         ///< access time for 2nd highest cas latency\r
+#define SPD_SDRAM_TCLK3_PULSE    25         ///< cycle time for 3rd highest cas latency\r
+#define SPD_SDRAM_TAC3_PULSE     26         ///< access time for 3rd highest cas latency\r
+#define SPD_SDRAM_MIN_PRECHARGE  27\r
+#define SPD_SDRAM_ACTIVE_MIN     28\r
+#define SPD_SDRAM_RAS_CAS        29\r
+#define SPD_SDRAM_RAS_PULSE      30\r
+#define SPD_SDRAM_DENSITY        31\r
 \r
 //\r
 // Memory Type Definitions\r
 //\r
-#define SPD_VAL_SDR_TYPE  4       ///< SDR SDRAM memory\r
-#define SPD_VAL_DDR_TYPE  7       ///< DDR SDRAM memory\r
-#define SPD_VAL_DDR2_TYPE 8       ///< DDR2 SDRAM memory\r
-#define SPD_VAL_DDR3_TYPE 11      ///< DDR3 SDRAM memory\r
-#define SPD_VAL_DDR4_TYPE 12      ///< DDR4 SDRAM memory\r
-#define SPD_VAL_LPDDR3_TYPE 15    ///< LPDDR3 SDRAM memory\r
-#define SPD_VAL_LPDDR4_TYPE 16    ///< LPDDR4 SDRAM memory\r
+#define SPD_VAL_SDR_TYPE     4    ///< SDR SDRAM memory\r
+#define SPD_VAL_DDR_TYPE     7    ///< DDR SDRAM memory\r
+#define SPD_VAL_DDR2_TYPE    8    ///< DDR2 SDRAM memory\r
+#define SPD_VAL_DDR3_TYPE    11   ///< DDR3 SDRAM memory\r
+#define SPD_VAL_DDR4_TYPE    12   ///< DDR4 SDRAM memory\r
+#define SPD_VAL_LPDDR3_TYPE  15   ///< LPDDR3 SDRAM memory\r
+#define SPD_VAL_LPDDR4_TYPE  16   ///< LPDDR4 SDRAM memory\r
 \r
 //\r
 // ECC Type Definitions\r
 //\r
-#define SPD_ECC_TYPE_NONE   0x00  ///< No error checking\r
-#define SPD_ECC_TYPE_PARITY 0x01  ///< No error checking\r
-#define SPD_ECC_TYPE_ECC    0x02  ///< Error checking only\r
+#define SPD_ECC_TYPE_NONE    0x00 ///< No error checking\r
+#define SPD_ECC_TYPE_PARITY  0x01 ///< No error checking\r
+#define SPD_ECC_TYPE_ECC     0x02 ///< Error checking only\r
 //\r
 // Module Attributes (Bit positions)\r
 //\r