Reviewed the description in the FatBinPkg .dec file.

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / SdramSpd.h

diff --git a/MdePkg/Include/IndustryStandard/SdramSpd.h b/MdePkg/Include/IndustryStandard/SdramSpd.h
index 59302ee7dae1c5fbc2ff60e38018409c0517ca7f..458e63b51fb13ab8c3df3053c11ea49bcd405bc4 100644 (file)
--- a/MdePkg/Include/IndustryStandard/SdramSpd.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -1,7 +1,7 @@
-/**@file\r
+/** @file\r
   This file contains definitions for the SPD fields on an SDRAM.\r
     \r
-  Copyright (c) 2007, Intel Corporation\r
+  Copyright (c) 2007 - 2008, Intel Corporation\r
   All rights reserved. This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -11,8 +11,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
 **/\r
 \r
-#ifndef _SDRAM_SPD_H\r
-#define _SDRAM_SPD_H\r
+#ifndef _SDRAM_SPD_H_\r
+#define _SDRAM_SPD_H_\r
 \r
 //\r
 // SDRAM SPD field definitions\r
@@ -32,12 +32,12 @@
 #define SPD_SDRAM_CAS_LATENCY           18\r
 #define SPD_SDRAM_MODULE_ATTR           21\r
 \r
-#define SPD_SDRAM_TCLK1_PULSE           9   // cycle time for highest cas latency\r
-#define SPD_SDRAM_TAC1_PULSE            10  // access time for highest cas latency\r
-#define SPD_SDRAM_TCLK2_PULSE           23  // cycle time for 2nd highest cas latency\r
-#define SPD_SDRAM_TAC2_PULSE            24  // access time for 2nd highest cas latency\r
-#define SPD_SDRAM_TCLK3_PULSE           25  // cycle time for 3rd highest cas latency\r
-#define SPD_SDRAM_TAC3_PULSE            26  // access time for 3rd highest cas latency\r
+#define SPD_SDRAM_TCLK1_PULSE           9   ///< cycle time for highest cas latency\r
+#define SPD_SDRAM_TAC1_PULSE            10  ///< access time for highest cas latency\r
+#define SPD_SDRAM_TCLK2_PULSE           23  ///< cycle time for 2nd highest cas latency\r
+#define SPD_SDRAM_TAC2_PULSE            24  ///< access time for 2nd highest cas latency\r
+#define SPD_SDRAM_TCLK3_PULSE           25  ///< cycle time for 3rd highest cas latency\r
+#define SPD_SDRAM_TAC3_PULSE            26  ///< access time for 3rd highest cas latency\r
 #define SPD_SDRAM_MIN_PRECHARGE         27\r
 #define SPD_SDRAM_ACTIVE_MIN            28\r
 #define SPD_SDRAM_RAS_CAS               29\r
@@ -47,15 +47,15 @@
 //\r
 // Memory Type Definitions\r
 //\r
-#define SPD_VAL_SDR_TYPE  4 // SDR SDRAM memory\r
-#define SPD_VAL_DDR_TYPE  7 // DDR SDRAM memory\r
-#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory\r
+#define SPD_VAL_SDR_TYPE  4 ///< SDR SDRAM memory\r
+#define SPD_VAL_DDR_TYPE  7 ///< DDR SDRAM memory\r
+#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory\r
 //\r
 // ECC Type Definitions\r
 //\r
-#define SPD_ECC_TYPE_NONE   0x00  // No error checking\r
-#define SPD_ECC_TYPE_PARITY 0x01  // No error checking\r
-#define SPD_ECC_TYPE_ECC    0x02  // Error checking only\r
+#define SPD_ECC_TYPE_NONE   0x00  ///< No error checking\r
+#define SPD_ECC_TYPE_PARITY 0x01  ///< No error checking\r
+#define SPD_ECC_TYPE_ECC    0x02  ///< Error checking only\r
 //\r
 // Module Attributes (Bit positions)\r
 //\r