/** @file\r
- Industry Standard Definitions of SMBIOS Table Specification v2.6.1\r
+ Industry Standard Definitions of SMBIOS Table Specification v3.1.0.\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials are licensed and made available under \r
the terms and conditions of the BSD License that accompanies this distribution. \r
The full text of the license may be found at\r
///\r
#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00\r
\r
+///\r
+/// Reference SMBIOS 2.7, chapter 6.1.2.\r
+/// The UEFI Platform Initialization Specification reserves handle number FFFEh for its\r
+/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."\r
+/// This number is not used for any other purpose by the SMBIOS specification.\r
+///\r
+#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE\r
+\r
///\r
/// Reference SMBIOS 2.6, chapter 3.1.3.\r
/// Each text string is limited to 64 significant characters due to system MIF limitations.\r
+/// Reference SMBIOS 2.7, chapter 6.1.3.\r
+/// It will have no limit on the length of each individual text string.\r
///\r
#define SMBIOS_STRING_MAX_LENGTH 64\r
\r
+//\r
+// The length of the entire structure table (including all strings) must be reported\r
+// in the Structure Table Length field of the SMBIOS Structure Table Entry Point,\r
+// which is a WORD field limited to 65,535 bytes.\r
+//\r
+#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF\r
+\r
+//\r
+// For SMBIOS 3.0, Structure table maximum size in Entry Point structure is DWORD field limited to 0xFFFFFFFF bytes.\r
+//\r
+#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF\r
+\r
+//\r
+// SMBIOS type macros which is according to SMBIOS 2.7 specification.\r
+//\r
+#define SMBIOS_TYPE_BIOS_INFORMATION 0\r
+#define SMBIOS_TYPE_SYSTEM_INFORMATION 1\r
+#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2\r
+#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3\r
+#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4\r
+#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5\r
+#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6\r
+#define SMBIOS_TYPE_CACHE_INFORMATION 7\r
+#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8\r
+#define SMBIOS_TYPE_SYSTEM_SLOTS 9\r
+#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10\r
+#define SMBIOS_TYPE_OEM_STRINGS 11\r
+#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12\r
+#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13\r
+#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14\r
+#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15\r
+#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16\r
+#define SMBIOS_TYPE_MEMORY_DEVICE 17\r
+#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18\r
+#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19\r
+#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20\r
+#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21\r
+#define SMBIOS_TYPE_PORTABLE_BATTERY 22\r
+#define SMBIOS_TYPE_SYSTEM_RESET 23\r
+#define SMBIOS_TYPE_HARDWARE_SECURITY 24\r
+#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25\r
+#define SMBIOS_TYPE_VOLTAGE_PROBE 26\r
+#define SMBIOS_TYPE_COOLING_DEVICE 27\r
+#define SMBIOS_TYPE_TEMPERATURE_PROBE 28\r
+#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29\r
+#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30\r
+#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31\r
+#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32\r
+#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33\r
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34\r
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35\r
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36\r
+#define SMBIOS_TYPE_MEMORY_CHANNEL 37\r
+#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38\r
+#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39\r
+#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40\r
+#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41\r
+#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42\r
+#define SMBIOS_TYPE_TPM_DEVICE 43\r
+\r
///\r
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.\r
/// Upper-level software that interprets the SMBIOS structure-table should bypass an \r
///\r
#define SMBIOS_TYPE_END_OF_TABLE 0x007F\r
\r
+#define SMBIOS_OEM_BEGIN 128\r
+#define SMBIOS_OEM_END 255\r
+\r
+///\r
+/// Types 0 through 127 (7Fh) are reserved for and defined by this\r
+/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information. \r
+///\r
+typedef UINT8 SMBIOS_TYPE;\r
+\r
+///\r
+/// Specifies the structure's handle, a unique 16-bit number in the range 0 to 0FFFEh (for version\r
+/// 2.0) or 0 to 0FEFFh (for version 2.1 and later). The handle can be used with the Get SMBIOS\r
+/// Structure function to retrieve a specific structure; the handle numbers are not required to be\r
+/// contiguous. For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for\r
+/// use by this specification.\r
+/// If the system configuration changes, a previously assigned handle might no longer exist.\r
+/// However once a handle has been assigned by the BIOS, the BIOS cannot re-assign that handle\r
+/// number to another structure.\r
+///\r
+typedef UINT16 SMBIOS_HANDLE;\r
+\r
///\r
/// Smbios Table Entry Point Structure.\r
///\r
UINT8 SmbiosBcdRevision;\r
} SMBIOS_TABLE_ENTRY_POINT;\r
\r
+typedef struct {\r
+ UINT8 AnchorString[5];\r
+ UINT8 EntryPointStructureChecksum;\r
+ UINT8 EntryPointLength;\r
+ UINT8 MajorVersion;\r
+ UINT8 MinorVersion;\r
+ UINT8 DocRev;\r
+ UINT8 EntryPointRevision;\r
+ UINT8 Reserved;\r
+ UINT32 TableMaximumSize;\r
+ UINT64 TableAddress;\r
+} SMBIOS_TABLE_3_0_ENTRY_POINT;\r
+\r
///\r
/// The Smbios structure header.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Handle;\r
+ SMBIOS_TYPE Type;\r
+ UINT8 Length;\r
+ SMBIOS_HANDLE Handle;\r
} SMBIOS_STRUCTURE;\r
\r
///\r
-/// String Number for a Null terminated string, 00h stands for no string available.\r
+/// Text strings associated with a given SMBIOS structure are returned in the dmiStrucBuffer, appended directly after\r
+/// the formatted portion of the structure. This method of returning string information eliminates the need for\r
+/// application software to deal with pointers embedded in the SMBIOS structure. Each string is terminated with a null\r
+/// (00h) BYTE and the set of strings is terminated with an additional null (00h) BYTE. When the formatted portion of\r
+/// a SMBIOS structure references a string, it does so by specifying a non-zero string number within the structure's\r
+/// string-set. For example, if a string field contains 02h, it references the second string following the formatted portion\r
+/// of the SMBIOS structure. If a string field references no string, a null (0) is placed in that string field. If the\r
+/// formatted portion of the structure contains string-reference fields and all the string fields are set to 0 (no string\r
+/// references), the formatted section of the structure is followed by two null (00h) BYTES.\r
///\r
typedef UINT8 SMBIOS_TABLE_STRING;\r
\r
///\r
-/// BIOS Characteristics \r
-/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc. \r
+/// BIOS Characteristics\r
+/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.\r
///\r
typedef struct {\r
UINT32 Reserved :2; ///< Bits 0-1.\r
- UINT32 Unknown :1; \r
- UINT32 BiosCharacteristicsNotSupported :1; \r
- UINT32 IsaIsSupported :1; \r
+ UINT32 Unknown :1;\r
+ UINT32 BiosCharacteristicsNotSupported :1;\r
+ UINT32 IsaIsSupported :1;\r
UINT32 McaIsSupported :1;\r
UINT32 EisaIsSupported :1;\r
UINT32 PciIsSupported :1;\r
} MISC_BIOS_CHARACTERISTICS;\r
\r
///\r
-/// BIOS Characteristics Extension Byte 1 .\r
-/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h \r
-/// within the BIOS Information structure.\r
+/// BIOS Characteristics Extension Byte 1.\r
+/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h\r
+/// within the BIOS Information structure.\r
///\r
typedef struct {\r
UINT8 AcpiIsSupported :1;\r
- UINT8 UsbLegacyIsSupported :1; \r
- UINT8 AgpIsSupported :1; \r
- UINT8 I20BootIsSupported :1;\r
+ UINT8 UsbLegacyIsSupported :1;\r
+ UINT8 AgpIsSupported :1;\r
+ UINT8 I2OBootIsSupported :1;\r
UINT8 Ls120BootIsSupported :1;\r
UINT8 AtapiZipDriveBootIsSupported :1;\r
UINT8 Boot1394IsSupported :1;\r
\r
///\r
/// BIOS Characteristics Extension Byte 2.\r
-/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h \r
+/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h\r
/// within the BIOS Information structure.\r
///\r
typedef struct {\r
UINT8 BiosBootSpecIsSupported :1;\r
- UINT8 FunctionKeyNetworkBootIsSupported :1; \r
- UINT8 TargetContentDistributionEnabled :1; \r
- UINT8 ExtensionByte2Reserved :1;\r
+ UINT8 FunctionKeyNetworkBootIsSupported :1;\r
+ UINT8 TargetContentDistributionEnabled :1;\r
+ UINT8 UefiSpecificationSupported :1;\r
+ UINT8 VirtualMachineSupported :1;\r
+ UINT8 ExtensionByte2Reserved :3;\r
} MBCE_SYSTEM_RESERVED;\r
\r
///\r
typedef struct {\r
MBCE_BIOS_RESERVED BiosReserved;\r
MBCE_SYSTEM_RESERVED SystemReserved;\r
- UINT8 Reserved;\r
} MISC_BIOS_CHARACTERISTICS_EXTENSION;\r
\r
+///\r
+/// Extended BIOS ROM size.\r
+///\r
+typedef struct {\r
+ UINT16 Size :14;\r
+ UINT16 Unit :2;\r
+} EXTENDED_BIOS_ROM_SIZE;\r
+\r
///\r
/// BIOS Information (Type 0).\r
///\r
UINT8 SystemBiosMinorRelease;\r
UINT8 EmbeddedControllerFirmwareMajorRelease;\r
UINT8 EmbeddedControllerFirmwareMinorRelease;\r
+ //\r
+ // Add for smbios 3.1.0\r
+ //\r
+ EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;\r
} SMBIOS_TABLE_TYPE0;\r
\r
///\r
MiscChassisCompactPCI = 0x1A,\r
MiscChassisAdvancedTCA = 0x1B,\r
MiscChassisBlade = 0x1C,\r
- MiscChassisBladeEnclosure = 0x1D\r
+ MiscChassisBladeEnclosure = 0x1D,\r
+ MiscChassisTablet = 0x1E,\r
+ MiscChassisConvertible = 0x1F,\r
+ MiscChassisDetachable = 0x20,\r
+ MiscChassisIoTGateway = 0x21,\r
+ MiscChassisEmbeddedPc = 0x22,\r
+ MiscChassisMiniPc = 0x23,\r
+ MiscChassisStickPc = 0x24\r
} MISC_CHASSIS_TYPE;\r
\r
///\r
UINT8 NumberofPowerCords;\r
UINT8 ContainedElementCount;\r
UINT8 ContainedElementRecordLength;\r
+ //\r
+ // Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements\r
+ //\r
CONTAINED_ELEMENT ContainedElements[1];\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ // Since ContainedElements has a variable number of entries, must not define SKUNumber in\r
+ // the structure. Need to reference it by starting at offset 0x15 and adding\r
+ // (ContainedElementCount * ContainedElementRecordLength) bytes.\r
+ //\r
+ // SMBIOS_TABLE_STRING SKUNumber;\r
} SMBIOS_TABLE_TYPE3;\r
\r
///\r
ProcessorFamilyPentiumIII = 0x11, \r
ProcessorFamilyM1 = 0x12,\r
ProcessorFamilyM2 = 0x13,\r
- ProcessorFamilyM1Reserved2 = 0x14,\r
- ProcessorFamilyM1Reserved3 = 0x15,\r
- ProcessorFamilyM1Reserved4 = 0x16,\r
- ProcessorFamilyM1Reserved5 = 0x17,\r
+ ProcessorFamilyIntelCeleronM = 0x14,\r
+ ProcessorFamilyIntelPentium4Ht = 0x15,\r
ProcessorFamilyAmdDuron = 0x18,\r
ProcessorFamilyK5 = 0x19, \r
ProcessorFamilyK6 = 0x1A,\r
ProcessorFamilyIntelCoreDuoMobile = 0x29,\r
ProcessorFamilyIntelCoreSoloMobile = 0x2A,\r
ProcessorFamilyIntelAtom = 0x2B,\r
- ProcessorFamilyAlpha3 = 0x30,\r
+ ProcessorFamilyIntelCoreM = 0x2C,\r
+ ProcessorFamilyIntelCorem3 = 0x2D,\r
+ ProcessorFamilyIntelCorem5 = 0x2E,\r
+ ProcessorFamilyIntelCorem7 = 0x2F,\r
+ ProcessorFamilyAlpha = 0x30,\r
ProcessorFamilyAlpha21064 = 0x31,\r
ProcessorFamilyAlpha21066 = 0x32,\r
ProcessorFamilyAlpha21164 = 0x33,\r
ProcessorFamilyAlpha21164a = 0x35,\r
ProcessorFamilyAlpha21264 = 0x36,\r
ProcessorFamilyAlpha21364 = 0x37,\r
+ ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,\r
+ ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,\r
+ ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,\r
+ ProcessorFamilyAmdOpteron6100Series = 0x3B,\r
+ ProcessorFamilyAmdOpteron4100Series = 0x3C,\r
+ ProcessorFamilyAmdOpteron6200Series = 0x3D,\r
+ ProcessorFamilyAmdOpteron4200Series = 0x3E,\r
+ ProcessorFamilyAmdFxSeries = 0x3F,\r
ProcessorFamilyMips = 0x40,\r
ProcessorFamilyMIPSR4000 = 0x41,\r
ProcessorFamilyMIPSR4200 = 0x42,\r
ProcessorFamilyMIPSR4400 = 0x43,\r
ProcessorFamilyMIPSR4600 = 0x44,\r
ProcessorFamilyMIPSR10000 = 0x45,\r
+ ProcessorFamilyAmdCSeries = 0x46,\r
+ ProcessorFamilyAmdESeries = 0x47,\r
+ ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name\r
+ ProcessorFamilyAmdGSeries = 0x49,\r
+ ProcessorFamilyAmdZSeries = 0x4A,\r
+ ProcessorFamilyAmdRSeries = 0x4B,\r
+ ProcessorFamilyAmdOpteron4300 = 0x4C,\r
+ ProcessorFamilyAmdOpteron6300 = 0x4D,\r
+ ProcessorFamilyAmdOpteron3300 = 0x4E,\r
+ ProcessorFamilyAmdFireProSeries = 0x4F,\r
ProcessorFamilySparc = 0x50,\r
ProcessorFamilySuperSparc = 0x51,\r
ProcessorFamilymicroSparcII = 0x52,\r
ProcessorFamilymicroSparcIIep = 0x53,\r
ProcessorFamilyUltraSparc = 0x54,\r
ProcessorFamilyUltraSparcII = 0x55,\r
- ProcessorFamilyUltraSparcIIi = 0x56,\r
+ ProcessorFamilyUltraSparcIii = 0x56,\r
ProcessorFamilyUltraSparcIII = 0x57,\r
ProcessorFamilyUltraSparcIIIi = 0x58,\r
ProcessorFamily68040 = 0x60,\r
ProcessorFamily68010 = 0x63,\r
ProcessorFamily68020 = 0x64,\r
ProcessorFamily68030 = 0x65,\r
+ ProcessorFamilyAmdAthlonX4QuadCore = 0x66,\r
+ ProcessorFamilyAmdOpteronX1000Series = 0x67,\r
+ ProcessorFamilyAmdOpteronX2000Series = 0x68,\r
+ ProcessorFamilyAmdOpteronASeries = 0x69,\r
+ ProcessorFamilyAmdOpteronX3000Series = 0x6A,\r
+ ProcessorFamilyAmdZen = 0x6B,\r
ProcessorFamilyHobbit = 0x70,\r
ProcessorFamilyCrusoeTM5000 = 0x78,\r
ProcessorFamilyCrusoeTM3000 = 0x79,\r
ProcessorFamilyIntelCeleronD = 0xBA,\r
ProcessorFamilyIntelPentiumD = 0xBB,\r
ProcessorFamilyIntelPentiumEx = 0xBC,\r
- ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 correct this value\r
+ ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value\r
ProcessorFamilyReserved = 0xBE,\r
ProcessorFamilyIntelCore2 = 0xBF,\r
ProcessorFamilyIntelCore2Solo = 0xC0,\r
ProcessorFamilyG4 = 0xC9,\r
ProcessorFamilyG5 = 0xCA,\r
ProcessorFamilyG6 = 0xCB,\r
- ProcessorFamilyzArchitectur = 0xCC,\r
+ ProcessorFamilyzArchitecture = 0xCC,\r
+ ProcessorFamilyIntelCoreI5 = 0xCD,\r
+ ProcessorFamilyIntelCoreI3 = 0xCE,\r
ProcessorFamilyViaC7M = 0xD2,\r
ProcessorFamilyViaC7D = 0xD3,\r
ProcessorFamilyViaC7 = 0xD4,\r
ProcessorFamilyMultiCoreIntelXeon = 0xD6,\r
ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,\r
ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,\r
+ ProcessorFamilyViaNano = 0xD9,\r
ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,\r
ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,\r
ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,\r
ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,\r
ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,\r
+ ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,\r
+ ProcessorFamilyAmdOpteron3000Series = 0xE4,\r
+ ProcessorFamilyAmdSempronII = 0xE5,\r
ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,\r
ProcessorFamilyAmdPhenomTripleCore = 0xE7,\r
ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,\r
ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,\r
ProcessorFamilyAmdAthlonDualCore = 0xEA,\r
ProcessorFamilyAmdSempronSI = 0xEB,\r
+ ProcessorFamilyAmdPhenomII = 0xEC,\r
+ ProcessorFamilyAmdAthlonII = 0xED,\r
+ ProcessorFamilySixCoreAmdOpteron = 0xEE,\r
+ ProcessorFamilyAmdSempronM = 0xEF,\r
ProcessorFamilyi860 = 0xFA,\r
ProcessorFamilyi960 = 0xFB,\r
ProcessorFamilyIndicatorFamily2 = 0xFE,\r
ProcessorFamilyReserved1 = 0xFF\r
} PROCESSOR_FAMILY_DATA;\r
\r
+///\r
+/// Processor Information2 - Processor Family2.\r
+///\r
+typedef enum {\r
+ ProcessorFamilyARMv7 = 0x0100,\r
+ ProcessorFamilyARMv8 = 0x0101,\r
+ ProcessorFamilySH3 = 0x0104,\r
+ ProcessorFamilySH4 = 0x0105,\r
+ ProcessorFamilyARM = 0x0118,\r
+ ProcessorFamilyStrongARM = 0x0119,\r
+ ProcessorFamily6x86 = 0x012C,\r
+ ProcessorFamilyMediaGX = 0x012D,\r
+ ProcessorFamilyMII = 0x012E,\r
+ ProcessorFamilyWinChip = 0x0140,\r
+ ProcessorFamilyDSP = 0x015E,\r
+ ProcessorFamilyVideoProcessor = 0x01F4\r
+} PROCESSOR_FAMILY2_DATA;\r
+\r
///\r
/// Processor Information - Voltage. \r
///\r
ProcessorUpgradeSocketS1 = 0x16,\r
ProcessorUpgradeAM2 = 0x17,\r
ProcessorUpgradeF1207 = 0x18,\r
- ProcessorSocketLGA1366 = 0x19\r
+ ProcessorSocketLGA1366 = 0x19,\r
+ ProcessorUpgradeSocketG34 = 0x1A,\r
+ ProcessorUpgradeSocketAM3 = 0x1B,\r
+ ProcessorUpgradeSocketC32 = 0x1C,\r
+ ProcessorUpgradeSocketLGA1156 = 0x1D,\r
+ ProcessorUpgradeSocketLGA1567 = 0x1E,\r
+ ProcessorUpgradeSocketPGA988A = 0x1F,\r
+ ProcessorUpgradeSocketBGA1288 = 0x20,\r
+ ProcessorUpgradeSocketrPGA988B = 0x21,\r
+ ProcessorUpgradeSocketBGA1023 = 0x22,\r
+ ProcessorUpgradeSocketBGA1224 = 0x23,\r
+ ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name\r
+ ProcessorUpgradeSocketLGA1356 = 0x25,\r
+ ProcessorUpgradeSocketLGA2011 = 0x26,\r
+ ProcessorUpgradeSocketFS1 = 0x27,\r
+ ProcessorUpgradeSocketFS2 = 0x28,\r
+ ProcessorUpgradeSocketFM1 = 0x29,\r
+ ProcessorUpgradeSocketFM2 = 0x2A,\r
+ ProcessorUpgradeSocketLGA2011_3 = 0x2B,\r
+ ProcessorUpgradeSocketLGA1356_3 = 0x2C,\r
+ ProcessorUpgradeSocketLGA1150 = 0x2D,\r
+ ProcessorUpgradeSocketBGA1168 = 0x2E,\r
+ ProcessorUpgradeSocketBGA1234 = 0x2F,\r
+ ProcessorUpgradeSocketBGA1364 = 0x30,\r
+ ProcessorUpgradeSocketAM4 = 0x31,\r
+ ProcessorUpgradeSocketLGA1151 = 0x32,\r
+ ProcessorUpgradeSocketBGA1356 = 0x33,\r
+ ProcessorUpgradeSocketBGA1440 = 0x34,\r
+ ProcessorUpgradeSocketBGA1515 = 0x35,\r
+ ProcessorUpgradeSocketLGA3647_1 = 0x36,\r
+ ProcessorUpgradeSocketSP3 = 0x37,\r
+ ProcessorUpgradeSocketSP3r2 = 0x38\r
} PROCESSOR_UPGRADE;\r
\r
///\r
// Add for smbios 2.6\r
//\r
UINT16 ProcessorFamily2;\r
+ //\r
+ // Add for smbios 3.0\r
+ //\r
+ UINT16 CoreCount2;\r
+ UINT16 EnabledCoreCount2;\r
+ UINT16 ThreadCount2;\r
} SMBIOS_TABLE_TYPE4;\r
\r
///\r
UINT16 NonBurst :1;\r
UINT16 Burst :1;\r
UINT16 PipelineBurst :1;\r
- UINT16 Asynchronous :1;\r
UINT16 Synchronous :1;\r
+ UINT16 Asynchronous :1;\r
UINT16 Reserved :9;\r
} CACHE_SRAM_TYPE_DATA;\r
\r
CacheAssociativity24Way = 0x0A,\r
CacheAssociativity32Way = 0x0B,\r
CacheAssociativity48Way = 0x0C,\r
- CacheAssociativity64Way = 0x0D\r
+ CacheAssociativity64Way = 0x0D,\r
+ CacheAssociativity20Way = 0x0E\r
} CACHE_ASSOCIATIVITY_DATA;\r
\r
///\r
UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.\r
UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.\r
UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.\r
+ //\r
+ // Add for smbios 3.1.0\r
+ //\r
+ UINT32 MaximumCacheSize2;\r
+ UINT32 InstalledSize2;\r
} SMBIOS_TABLE_TYPE7;\r
\r
///\r
PortConnectorTypeRJ45 = 0x0B,\r
PortConnectorType50PinMiniScsi = 0x0C,\r
PortConnectorTypeMiniDin = 0x0D,\r
- PortConnectorTypeMicriDin = 0x0E,\r
+ PortConnectorTypeMicroDin = 0x0E,\r
PortConnectorTypePS2 = 0x0F,\r
PortConnectorTypeInfrared = 0x10,\r
PortConnectorTypeHpHil = 0x11,\r
PortConnectorTypeHeadPhoneMiniJack = 0x1F,\r
PortConnectorTypeBNC = 0x20,\r
PortConnectorType1394 = 0x21,\r
+ PortConnectorTypeSasSata = 0x22,\r
PortConnectorTypePC98 = 0xA0,\r
PortConnectorTypePC98Hireso = 0xA1,\r
PortConnectorTypePCH98 = 0xA2,\r
PortTypeAudioPort = 0x1D,\r
PortTypeModemPort = 0x1E,\r
PortTypeNetworkPort = 0x1F,\r
+ PortTypeSata = 0x20,\r
+ PortTypeSas = 0x21,\r
PortType8251Compatible = 0xA0,\r
PortType8251FifoCompatible = 0xA1,\r
PortTypeOther = 0xFF\r
SlotTypeApg2X = 0x10,\r
SlotTypeAgp4X = 0x11,\r
SlotTypePciX = 0x12,\r
- SlotTypeAgp4x = 0x13,\r
+ SlotTypeAgp8X = 0x13,\r
+ SlotTypeM2Socket1_DP = 0x14,\r
+ SlotTypeM2Socket1_SD = 0x15,\r
+ SlotTypeM2Socket2 = 0x16,\r
+ SlotTypeM2Socket3 = 0x17,\r
+ SlotTypeMxmTypeI = 0x18,\r
+ SlotTypeMxmTypeII = 0x19,\r
+ SlotTypeMxmTypeIIIStandard = 0x1A,\r
+ SlotTypeMxmTypeIIIHe = 0x1B,\r
+ SlotTypeMxmTypeIV = 0x1C,\r
+ SlotTypeMxm30TypeA = 0x1D,\r
+ SlotTypeMxm30TypeB = 0x1E,\r
+ SlotTypePciExpressGen2Sff_8639 = 0x1F,\r
+ SlotTypePciExpressGen3Sff_8639 = 0x20,\r
+ SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.\r
+ SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.\r
+ SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.\r
SlotTypePC98C20 = 0xA0,\r
SlotTypePC98C24 = 0xA1,\r
SlotTypePC98E = 0xA2,\r
SlotTypePciExpressGen2X2 = 0xAD,\r
SlotTypePciExpressGen2X4 = 0xAE,\r
SlotTypePciExpressGen2X8 = 0xAF,\r
- SlotTypePciExpressGen2X16 = 0xB0\r
+ SlotTypePciExpressGen2X16 = 0xB0,\r
+ SlotTypePciExpressGen3 = 0xB1,\r
+ SlotTypePciExpressGen3X1 = 0xB2,\r
+ SlotTypePciExpressGen3X2 = 0xB3,\r
+ SlotTypePciExpressGen3X4 = 0xB4,\r
+ SlotTypePciExpressGen3X8 = 0xB5,\r
+ SlotTypePciExpressGen3X16 = 0xB6\r
} MISC_SLOT_TYPE;\r
\r
///\r
OnBoardDeviceTypeScsiController = 0x04,\r
OnBoardDeviceTypeEthernet = 0x05,\r
OnBoardDeviceTypeTokenRing = 0x06,\r
- OnBoardDeviceTypeSound = 0x07\r
+ OnBoardDeviceTypeSound = 0x07,\r
+ OnBoardDeviceTypePATAController = 0x08,\r
+ OnBoardDeviceTypeSATAController = 0x09,\r
+ OnBoardDeviceTypeSASController = 0x0A\r
} MISC_ONBOARD_DEVICE_TYPE;\r
\r
///\r
SMBIOS_TABLE_STRING CurrentLanguages;\r
} SMBIOS_TABLE_TYPE13;\r
\r
+///\r
+/// Group Item Entry\r
+///\r
+typedef struct {\r
+ UINT8 ItemType;\r
+ UINT16 ItemHandle;\r
+} GROUP_STRUCT;\r
+\r
+///\r
+/// Group Associations (Type 14).\r
+///\r
+/// The Group Associations structure is provided for OEMs who want to specify \r
+/// the arrangement or hierarchy of certain components (including other Group Associations) \r
+/// within the system. \r
+///\r
+typedef struct {\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING GroupName;\r
+ GROUP_STRUCT Group[1];\r
+} SMBIOS_TABLE_TYPE14;\r
+\r
///\r
/// System Event Log - Event Log Types.\r
/// \r
EventLogVariableOEMAssigned = 0x80\r
} EVENT_LOG_VARIABLE_DATA;\r
\r
-///\r
-/// Group Item Entry\r
-///\r
-typedef struct {\r
- UINT8 ItemType;\r
- UINT16 ItemHandle;\r
-} GROUP_STRUCT;\r
-\r
///\r
/// Event Log Type Descriptors\r
///\r
UINT8 DataFormatType;\r
} EVENT_LOG_TYPE;\r
\r
-///\r
-/// Group Associations (Type 14).\r
-///\r
-/// The Group Associations structure is provided for OEMs who want to specify \r
-/// the arrangement or hierarchy of certain components (including other Group Associations) \r
-/// within the system. \r
-///\r
-typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING GroupName;\r
- GROUP_STRUCT Group[1];\r
-} SMBIOS_TABLE_TYPE14;\r
-\r
///\r
/// System Event Log (Type 15).\r
///\r
UINT32 MaximumCapacity;\r
UINT16 MemoryErrorInformationHandle;\r
UINT16 NumberOfMemoryDevices;\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ UINT64 ExtendedMaximumCapacity;\r
} SMBIOS_TABLE_TYPE16;\r
\r
///\r
MemoryTypeDdr2 = 0x13,\r
MemoryTypeDdr2FbDimm = 0x14,\r
MemoryTypeDdr3 = 0x18,\r
- MemoryTypeFbd2 = 0x19\r
+ MemoryTypeFbd2 = 0x19,\r
+ MemoryTypeDdr4 = 0x1A,\r
+ MemoryTypeLpddr = 0x1B,\r
+ MemoryTypeLpddr2 = 0x1C,\r
+ MemoryTypeLpddr3 = 0x1D,\r
+ MemoryTypeLpddr4 = 0x1E\r
} MEMORY_DEVICE_TYPE;\r
\r
typedef struct {\r
UINT16 WindowDram :1;\r
UINT16 CacheDram :1;\r
UINT16 Nonvolatile :1;\r
- UINT16 Reserved1 :3;\r
+ UINT16 Registered :1;\r
+ UINT16 Unbuffered :1;\r
+ UINT16 LrDimm :1;\r
} MEMORY_DEVICE_TYPE_DETAIL;\r
\r
///\r
//\r
// Add for smbios 2.6\r
// \r
- UINT8 Attributes;\r
+ UINT8 Attributes;\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ UINT32 ExtendedSize;\r
+ UINT16 ConfiguredMemoryClockSpeed;\r
+ //\r
+ // Add for smbios 2.8.0\r
+ //\r
+ UINT16 MinimumVoltage;\r
+ UINT16 MaximumVoltage;\r
+ UINT16 ConfiguredVoltage;\r
} SMBIOS_TABLE_TYPE17;\r
\r
///\r
UINT32 EndingAddress;\r
UINT16 MemoryArrayHandle;\r
UINT8 PartitionWidth;\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ UINT64 ExtendedStartingAddress;\r
+ UINT64 ExtendedEndingAddress;\r
} SMBIOS_TABLE_TYPE19;\r
\r
///\r
UINT8 PartitionRowPosition;\r
UINT8 InterleavePosition;\r
UINT8 InterleavedDataDepth;\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ UINT64 ExtendedStartingAddress;\r
+ UINT64 ExtendedEndingAddress;\r
} SMBIOS_TABLE_TYPE20;\r
\r
///\r
UINT8 CoolingUnitGroup;\r
UINT32 OEMDefined;\r
UINT16 NominalSpeed;\r
+ //\r
+ // Add for smbios 2.7\r
+ //\r
+ SMBIOS_TABLE_STRING Description;\r
} SMBIOS_TABLE_TYPE27;\r
\r
///\r
///\r
/// IPMI Device Information (Type 38).\r
///\r
-/// The information in this structure defines the attributes of an \r
+/// The information in this structure defines the attributes of an\r
/// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC).\r
-/// \r
+///\r
+/// The Type 42 structure can also be used to describe a physical management controller\r
+/// host interface and one or more protocols that share that interface. If IPMI is not\r
+/// shared with other protocols, either the Type 38 or Type 42 structures can be used.\r
+/// Providing Type 38 is recommended for backward compatibility.\r
+///\r
typedef struct {\r
SMBIOS_STRUCTURE Hdr;\r
UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.\r
///\r
/// System Power Supply (Type 39).\r
///\r
-/// This structure identifies attributes of a system power supply. One instance\r
-/// of this record is present for each possible power supply in a system. \r
+/// This structure identifies attributes of a system power supply. One instance\r
+/// of this record is present for each possible power supply in a system.\r
///\r
typedef struct {\r
SMBIOS_STRUCTURE Hdr;\r
UINT8 DeviceTypeInstance;\r
UINT16 SegmentGroupNum;\r
UINT8 BusNum;\r
- UINT8 DevFuncNum; \r
+ UINT8 DevFuncNum;\r
} SMBIOS_TABLE_TYPE41;\r
\r
+///\r
+/// Management Controller Host Interface - Interface Types.\r
+/// 00h - 3Fh: MCTP Host Interfaces\r
+///\r
+typedef enum{\r
+ MCHostInterfaceTypeNetworkHostInterface = 0x40,\r
+ MCHostInterfaceTypeOemDefined = 0xF0\r
+} MC_HOST_INTERFACE_TYPE;\r
+\r
+///\r
+/// Management Controller Host Interface - Protocol Types.\r
+///\r
+typedef enum{\r
+ MCHostInterfaceProtocolTypeIPMI = 0x02,\r
+ MCHostInterfaceProtocolTypeMCTP = 0x03,\r
+ MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,\r
+ MCHostInterfaceProtocolTypeOemDefined = 0xF0\r
+} MC_HOST_INTERFACE_PROTOCOL_TYPE;\r
+\r
+///\r
+/// Management Controller Host Interface (Type 42).\r
+///\r
+/// The information in this structure defines the attributes of a Management\r
+/// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms.\r
+///\r
+/// Type 42 should be used for management controller host interfaces that use protocols\r
+/// other than IPMI or that use multiple protocols on a single host interface type.\r
+///\r
+/// This structure should also be provided if IPMI is shared with other protocols\r
+/// over the same interface hardware. If IPMI is not shared with other protocols,\r
+/// either the Type 38 or Type 42 structures can be used. Providing Type 38 is\r
+/// recommended for backward compatibility. The structures are not required to\r
+/// be mutually exclusive. Type 38 and Type 42 structures may be implemented\r
+/// simultaneously to provide backward compatibility with IPMI applications or drivers\r
+/// that do not yet recognize the Type 42 structure.\r
+///\r
+typedef struct {\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE\r
+ UINT8 MCHostInterfaceData[1]; ///< This field has a minimum of four bytes\r
+} SMBIOS_TABLE_TYPE42;\r
+\r
+///\r
+/// TPM Device (Type 43).\r
+///\r
+typedef struct {\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 VendorID[4];\r
+ UINT8 MajorSpecVersion;\r
+ UINT8 MinorSpecVersion;\r
+ UINT32 FirmwareVersion1;\r
+ UINT32 FirmwareVersion2;\r
+ SMBIOS_TABLE_STRING Description;\r
+ UINT64 Characteristics;\r
+ UINT32 OemDefined;\r
+} SMBIOS_TABLE_TYPE43;\r
+\r
///\r
/// Inactive (Type 126)\r
///\r
SMBIOS_TABLE_TYPE39 *Type39;\r
SMBIOS_TABLE_TYPE40 *Type40;\r
SMBIOS_TABLE_TYPE41 *Type41;\r
+ SMBIOS_TABLE_TYPE42 *Type42;\r
+ SMBIOS_TABLE_TYPE43 *Type43;\r
SMBIOS_TABLE_TYPE126 *Type126;\r
SMBIOS_TABLE_TYPE127 *Type127;\r
UINT8 *Raw;\r
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