///\r
/// Used to gain ownership for this particular port.\r
///\r
- UINT8 Access; // 0\r
- UINT8 Reserved1[7]; // 1\r
+ UINT8 Access; // 0\r
+ UINT8 Reserved1[7]; // 1\r
///\r
/// Controls interrupts.\r
///\r
- UINT32 IntEnable; // 8\r
+ UINT32 IntEnable; // 8\r
///\r
/// SIRQ vector to be used by the TPM.\r
///\r
- UINT8 IntVector; // 0ch\r
- UINT8 Reserved2[3]; // 0dh\r
+ UINT8 IntVector; // 0ch\r
+ UINT8 Reserved2[3]; // 0dh\r
///\r
/// What caused interrupt.\r
///\r
- UINT32 IntSts; // 10h\r
+ UINT32 IntSts; // 10h\r
///\r
/// Shows which interrupts are supported by that particular TPM.\r
///\r
- UINT32 IntfCapability; // 14h\r
+ UINT32 IntfCapability; // 14h\r
///\r
/// Status Register. Provides status of the TPM.\r
///\r
- UINT8 Status; // 18h\r
+ UINT8 Status; // 18h\r
///\r
/// Number of consecutive writes that can be done to the TPM.\r
///\r
- UINT16 BurstCount; // 19h\r
- UINT8 Reserved3[9];\r
+ UINT16 BurstCount; // 19h\r
+ UINT8 Reserved3[9];\r
///\r
/// Read or write FIFO, depending on transaction.\r
///\r
- UINT32 DataFifo; // 24h\r
- UINT8 Reserved4[0xed8]; // 28h\r
+ UINT32 DataFifo; // 24h\r
+ UINT8 Reserved4[0xed8]; // 28h\r
///\r
/// Vendor ID\r
///\r
- UINT16 Vid; // 0f00h\r
+ UINT16 Vid; // 0f00h\r
///\r
/// Device ID\r
///\r
- UINT16 Did; // 0f02h\r
+ UINT16 Did; // 0f02h\r
///\r
/// Revision ID\r
///\r
- UINT8 Rid; // 0f04h\r
- UINT8 Reserved[0x7b]; // 0f05h\r
+ UINT8 Rid; // 0f04h\r
+ UINT8 Reserved[0x7b]; // 0f05h\r
///\r
/// Alias to I/O legacy space.\r
///\r
- UINT32 LegacyAddress1; // 0f80h\r
+ UINT32 LegacyAddress1; // 0f80h\r
///\r
/// Additional 8 bits for I/O legacy space extension.\r
///\r
- UINT32 LegacyAddress1Ex; // 0f84h\r
+ UINT32 LegacyAddress1Ex; // 0f84h\r
///\r
/// Alias to second I/O legacy space.\r
///\r
- UINT32 LegacyAddress2; // 0f88h\r
+ UINT32 LegacyAddress2; // 0f88h\r
///\r
/// Additional 8 bits for second I/O legacy space extension.\r
///\r
- UINT32 LegacyAddress2Ex; // 0f8ch\r
+ UINT32 LegacyAddress2Ex; // 0f8ch\r
///\r
/// Vendor-defined configuration registers.\r
///\r
- UINT8 VendorDefined[0x70];// 0f90h\r
+ UINT8 VendorDefined[0x70]; // 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
-typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
+typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
-#define TIS_PC_VALID BIT7\r
+#define TIS_PC_VALID BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
-#define TIS_PC_ACC_ACTIVE BIT5\r
+#define TIS_PC_ACC_ACTIVE BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
-#define TIS_PC_ACC_SEIZED BIT4\r
+#define TIS_PC_ACC_SEIZED BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
-#define TIS_PC_ACC_SEIZE BIT3\r
+#define TIS_PC_ACC_SEIZE BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
-#define TIS_PC_ACC_PENDIND BIT2\r
+#define TIS_PC_ACC_PENDIND BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
-#define TIS_PC_ACC_RQUUSE BIT1\r
+#define TIS_PC_ACC_RQUUSE BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
-#define TIS_PC_ACC_ESTABLISH BIT0\r
+#define TIS_PC_ACC_ESTABLISH BIT0\r
\r
///\r
/// Write a 1 to this bit to notify TPM to cancel currently executing command\r
///\r
-#define TIS_PC_STS_CANCEL BIT24\r
+#define TIS_PC_STS_CANCEL BIT24\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
-#define TIS_PC_STS_VALID BIT7\r
+#define TIS_PC_STS_VALID BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
-#define TIS_PC_STS_READY BIT6\r
+#define TIS_PC_STS_READY BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
-#define TIS_PC_STS_GO BIT5\r
+#define TIS_PC_STS_GO BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
-#define TIS_PC_STS_DATA BIT4\r
+#define TIS_PC_STS_DATA BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
-#define TIS_PC_STS_EXPECT BIT3\r
+#define TIS_PC_STS_EXPECT BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
-#define TIS_PC_STS_SELFTEST_DONE BIT2\r
+#define TIS_PC_STS_SELFTEST_DONE BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
-#define TIS_PC_STS_RETRY BIT1\r
+#define TIS_PC_STS_RETRY BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
-#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
-#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
-#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
-#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
+#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff