/**\r
Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
\r
+ Performs an atomic compare exchange operation on the 32-bit unsigned integer\r
+ specified by Value. If Value is equal to CompareValue, then Value is set to\r
+ ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,\r
+ then Value is returned. The compare exchange operation must be performed using\r
+ MP safe mechanisms.\r
+\r
+ If Value is NULL, then ASSERT().\r
+\r
@param Value A pointer to the 32-bit value for the compare exchange\r
operation.\r
@param CompareValue 32-bit value used in compare operation.\r
/**\r
Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
\r
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified\r
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and\r
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.\r
+ The compare exchange operation must be performed using MP safe mechanisms.\r
+\r
+ If Value is NULL, then ASSERT().\r
+\r
@param Value A pointer to the 64-bit value for the compare exchange\r
operation.\r
@param CompareValue 64-bit value used in compare operation.\r
calls to LongJump() cause a non-zero value to be returned by SetJump().\r
\r
If JumpBuffer is NULL, then ASSERT().\r
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
\r
the state of JumpBuffer.\r
\r
If JumpBuffer is NULL, then ASSERT().\r
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
If Value is 0, then ASSERT().\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
IN OUT THUNK_CONTEXT *ThunkContext\r
);\r
\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param NewBsp A pointer to the new memory location for RSE backing\r
+ store.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmSwitchStackAndBackingStore (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ IN VOID *NewBsp\r
+ );\r
+\r
+typedef struct {\r
+ UINT64 Status;\r
+ UINT64 r9;\r
+ UINT64 r10;\r
+ UINT64 r11;\r
+} PAL_PROC_RETURN;\r
+\r
+//\r
+// IPF Specific functions\r
+//\r
+\r
+\r
+/**\r
+ Performs a PAL call using static calling convention.\r
+\r
+ An internal function to perform a PAL call using static calling convention.\r
+\r
+ @param PalEntryPoint The entry point address of PAL. The address in ar.kr5\r
+ would be used if this parameter were NULL on input.\r
+ @param Arg1 The first argument of a PAL call.\r
+ @param Arg1 The second argument of a PAL call.\r
+ @param Arg1 The third argument of a PAL call.\r
+ @param Arg1 The fourth argument of a PAL call.\r
+\r
+ @return The values returned in r8, r9, r10 and r11.\r
+\r
+**/\r
+PAL_PROC_RETURN\r
+PalCallStatic (\r
+ IN CONST VOID *PalEntryPoint,\r
+ IN UINT64 Arg1,\r
+ IN UINT64 Arg2,\r
+ IN UINT64 Arg3,\r
+ IN UINT64 Arg4\r
+ );\r
+\r
+\r
+/**\r
+ Returns the current value of ar.itc.\r
+\r
+ An internal function to return the current value of ar.itc, which is the\r
+ timer tick on IPF.\r
+\r
+ @return The currect value of ar.itc\r
+\r
+**/\r
+INT64\r
+IpfReadItc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Flush a range of cache lines in the cache coherency domain of the calling \r
+ CPU.\r
+\r
+ Invalidates the cache lines specified by Address and Length. If Address is \r
+ not aligned on a cache line boundary, then entire cache line containing \r
+ Address is invalidated. If Address + Length is not aligned on a cache line \r
+ boundary, then the entire instruction cache line containing Address + Length\r
+ -1 is invalidated. This function may choose to invalidate the entire \r
+ instruction cache if that is more efficient than invalidating the specified \r
+ range. If Length is 0, the no instruction cache lines are invalidated. \r
+ Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction lines to invalidate. If \r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing mode,\r
+ then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+IpfFlushCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r
#endif\r
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