+ @return The bit field read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldRead64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ );\r
+\r
+\r
+/**\r
+ Writes a bit field to a 64-bit value, and returns the result.\r
+\r
+ Writes Value to the bit field specified by the StartBit and the EndBit in\r
+ Operand. All other bits in Operand are preserved. The new 64-bit value is\r
+ returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldWrite64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the\r
+ result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
+ and EndBit in Operand and the value specified by OrData. All other bits in\r
+ Operand are preserved. The new 64-bit value is returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param OrData The value to OR with the read value from the value\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldOr64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
+ );\r
+\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, performs a bitwise AND, and returns\r
+ the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new 64-bit value is returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the value\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldAnd64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
+ );\r
+\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, performs a bitwise AND followed by a\r
+ bitwise OR, and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
+ preserved. The new 64-bit value is returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the value.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldAndThenOr64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ );\r
+\r
+//\r
+// Base Library Checksum Functions\r
+//\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer in unit of UINT8.\r
+ During calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of all elements in a buffer\r
+ in unit of UINT8. The carry bits in result of addition are dropped.\r
+ The result is returned as UINT8. If Length is Zero, then Zero is\r
+ returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CalculateSum8 (\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer\r
+ of 8-bit values.\r
+\r
+ This function first calculates the sum of the 8-bit values in the\r
+ buffer specified by Buffer and Length. The carry bits in the result\r
+ of addition are dropped. Then, the two's complement of the sum is\r
+ returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The two's complement checksum of Buffer.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CalculateCheckSum8 (\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 16-bit values. During\r
+ calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of the 16-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in result of addition are dropped.\r
+ The 16-bit result is returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+CalculateSum16 (\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer of\r
+ 16-bit values.\r
+\r
+ This function first calculates the sum of the 16-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in the result of addition\r
+ are dropped. Then, the two's complement of the sum is returned. If Length\r
+ is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The two's complement checksum of Buffer.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+CalculateCheckSum16 (\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 32-bit values. During\r
+ calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of the 32-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in result of addition are dropped.\r
+ The 32-bit result is returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+CalculateSum32 (\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer of\r
+ 32-bit values.\r
+\r
+ This function first calculates the sum of the 32-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in the result of addition\r
+ are dropped. Then, the two's complement of the sum is returned. If Length\r
+ is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The two's complement checksum of Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+CalculateCheckSum32 (\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 64-bit values. During\r
+ calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of the 64-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in result of addition are dropped.\r
+ The 64-bit result is returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+CalculateSum64 (\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer of\r
+ 64-bit values.\r
+\r
+ This function first calculates the sum of the 64-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in the result of addition\r
+ are dropped. Then, the two's complement of the sum is returned. If Length\r
+ is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The two's complement checksum of Buffer.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+CalculateCheckSum64 (\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+//\r
+// Base Library CPU Functions\r
+//\r
+\r
+/**\r
+ Function entry point used when a stack switch is requested with SwitchStack()\r
+\r
+ @param Context1 Context1 parameter passed into SwitchStack().\r
+ @param Context2 Context2 parameter passed into SwitchStack().\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *SWITCH_STACK_ENTRY_POINT)(\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2 OPTIONAL\r
+ );\r
+\r
+\r
+/**\r
+ Used to serialize load and store operations.\r
+\r
+ All loads and stores that proceed calls to this function are guaranteed to be\r
+ globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Saves the current CPU context that can be restored with a call to LongJump()\r
+ and returns 0.\r
+\r
+ Saves the current CPU context in the buffer specified by JumpBuffer and\r
+ returns 0. The initial call to SetJump() must always return 0. Subsequent\r
+ calls to LongJump() cause a non-zero value to be returned by SetJump().\r
+\r
+ If JumpBuffer is NULL, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ \r
+ NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.\r
+ The same structure must never be used for more than one CPU architecture context.\r
+ For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module. \r
+ SetJump()/LongJump() is not currently supported for the EBC processor type. \r
+\r
+ @param JumpBuffer A pointer to CPU context buffer.\r
+\r
+ @retval 0 Indicates a return from SetJump().\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SetJump (\r
+ OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ );\r
+\r
+\r
+/**\r
+ Restores the CPU context that was saved with SetJump().\r
+\r
+ Restores the CPU context from the buffer specified by JumpBuffer. This\r
+ function never returns to the caller. Instead is resumes execution based on\r
+ the state of JumpBuffer.\r
+\r
+ If JumpBuffer is NULL, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ If Value is 0, then ASSERT().\r
+\r
+ @param JumpBuffer A pointer to CPU context buffer.\r
+ @param Value The value to return when the SetJump() context is\r
+ restored and must be non-zero.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+LongJump (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+ IN UINTN Value\r
+ );\r
+\r
+\r
+/**\r
+ Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Disables CPU interrupts and returns the interrupt state prior to the disable\r
+ operation.\r
+\r
+ @retval TRUE CPU interrupts were enabled on entry to this call.\r
+ @retval FALSE CPU interrupts were disabled on entry to this call.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SaveAndDisableInterrupts (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Enables CPU interrupts for the smallest window required to capture any\r
+ pending interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableDisableInterrupts (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Retrieves the current CPU interrupt state.\r
+\r
+ Returns TRUE if interrupts are currently enabled. Otherwise\r
+ returns FALSE.\r
+\r
+ @retval TRUE CPU interrupts are enabled.\r
+ @retval FALSE CPU interrupts are disabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+GetInterruptState (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Set the current CPU interrupt state.\r
+\r
+ Sets the current CPU interrupt state to the state specified by\r
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If\r
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is\r
+ returned.\r
+\r
+ @param InterruptState TRUE if interrupts should enabled. FALSE if\r
+ interrupts should be disabled.\r
+\r
+ @return InterruptState\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SetInterruptState (\r
+ IN BOOLEAN InterruptState\r
+ );\r
+\r
+\r
+/**\r
+ Requests CPU to pause for a short period of time.\r
+\r
+ Requests CPU to pause for a short period of time. Typically used in MP\r
+ systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the\r
+ new stack specified by NewStack and passing in the parameters specified\r
+ by Context1 and Context2. Context1 and Context2 are optional and may\r
+ be NULL. The function EntryPoint must never return. This function\r
+ supports a variable number of arguments following the NewStack parameter.\r
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.\r
+ Itanium processors expect one additional parameter of type VOID * that specifies\r
+ the new backing store pointer.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param ... This variable argument list is ignored for IA-32, x64, and \r
+ EBC architectures. For Itanium processors, this variable \r
+ argument list is expected to contain a single parameter of \r
+ type VOID * that specifies the new backing store pointer.\r
+\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SwitchStack (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ ...\r
+ );\r
+\r
+\r
+/**\r
+ Generates a breakpoint on the CPU.\r
+\r
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+ that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Executes an infinite loop.\r
+\r
+ Forces the CPU to execute an infinite loop. A debugger may be used to skip\r
+ past the loop and the code that follows the loop must execute properly. This\r
+ implies that the infinite loop must not cause the code that follow it to be\r
+ optimized away.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuDeadLoop (\r
+ VOID\r
+ );\r
+ \r
+#if defined (MDE_CPU_IPF)\r
+\r
+/**\r
+ Flush a range of cache lines in the cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Flushes the cache lines specified by Address and Length. If Address is not aligned \r
+ on a cache line boundary, then entire cache line containing Address is flushed. \r
+ If Address + Length is not aligned on a cache line boundary, then the entire cache \r
+ line containing Address + Length - 1 is flushed. This function may choose to flush \r
+ the entire cache if that is more efficient than flushing the specified range. If \r
+ Length is 0, the no cache lines are flushed. Address is returned. \r
+ This function is only available on Itanium processors.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction lines to invalidate. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing mode,\r
+ then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+AsmFlushCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Executes an FC instruction.\r
+ Executes an FC instruction on the cache line specified by Address.\r
+ The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
+\r
+ @param Address The Address of cache line to be flushed.\r
+\r
+ @return The address of FC instruction executed.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmFc (\r
+ IN UINT64 Address\r
+ );\r
+\r
+\r
+/**\r
+ Executes an FC.I instruction.\r
+ Executes an FC.I instruction on the cache line specified by Address.\r
+ The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
+\r
+ @param Address The Address of cache line to be flushed.\r
+\r
+ @return The address of the FC.I instruction executed.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmFci (\r
+ IN UINT64 Address\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of a Processor Identifier Register (CPUID).\r
+ \r
+ Reads and returns the current value of Processor Identifier Register specified by Index. \r
+ The Index of largest implemented CPUID (One less than the number of implemented CPUID\r
+ registers) is determined by CPUID [3] bits {7:0}.\r
+ No parameter checking is performed on Index. If the Index value is beyond the\r
+ implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
+ must either guarantee that Index is valid, or the caller must set up fault handlers to\r
+ catch the faults. This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Processor Identifier Register index to read.\r
+\r
+ @return The current value of Processor Identifier Register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadCpuid (\r
+ IN UINT8 Index\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Processor Status Register (PSR).\r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of PSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPsr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Processor Status Register (PSR).\r
+\r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to PSR.\r
+\r
+ @return The 64-bit value written to the PSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWritePsr (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #0 (KR0).\r
+ \r
+ Reads and returns the current value of KR0. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr0 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #1 (KR1).\r
+\r
+ Reads and returns the current value of KR1. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #2 (KR2).\r
+\r
+ Reads and returns the current value of KR2. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr2 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #3 (KR3).\r
+\r
+ Reads and returns the current value of KR3. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr3 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #4 (KR4).\r
+\r
+ Reads and returns the current value of KR4. \r
+ This function is only available on Itanium processors.\r
+ \r
+ @return The current value of KR4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr4 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #5 (KR5).\r
+\r
+ Reads and returns the current value of KR5. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr5 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #6 (KR6).\r
+\r
+ Reads and returns the current value of KR6. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr6 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #7 (KR7).\r
+\r
+ Reads and returns the current value of KR7. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr7 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #0 (KR0).\r
+ \r
+ Writes the current value of KR0. The 64-bit value written to \r
+ the KR0 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR0.\r
+\r
+ @return The 64-bit value written to the KR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr0 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #1 (KR1).\r
+\r
+ Writes the current value of KR1. The 64-bit value written to \r
+ the KR1 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR1.\r
+\r
+ @return The 64-bit value written to the KR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr1 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #2 (KR2).\r
+\r
+ Writes the current value of KR2. The 64-bit value written to \r
+ the KR2 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR2.\r
+\r
+ @return The 64-bit value written to the KR2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr2 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #3 (KR3).\r
+\r
+ Writes the current value of KR3. The 64-bit value written to \r
+ the KR3 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR3.\r
+\r
+ @return The 64-bit value written to the KR3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr3 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #4 (KR4).\r
+\r
+ Writes the current value of KR4. The 64-bit value written to \r
+ the KR4 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR4.\r
+\r
+ @return The 64-bit value written to the KR4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr4 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #5 (KR5).\r
+\r
+ Writes the current value of KR5. The 64-bit value written to \r
+ the KR5 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR5.\r
+\r
+ @return The 64-bit value written to the KR5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr5 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #6 (KR6).\r
+\r
+ Writes the current value of KR6. The 64-bit value written to \r
+ the KR6 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR6.\r
+\r
+ @return The 64-bit value written to the KR6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr6 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #7 (KR7).\r
+\r
+ Writes the current value of KR7. The 64-bit value written to \r
+ the KR7 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR7.\r
+\r
+ @return The 64-bit value written to the KR7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr7 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interval Timer Counter Register (ITC).\r
+ \r
+ Reads and returns the current value of ITC.\r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of ITC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadItc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interval Timer Vector Register (ITV).\r
+ \r
+ Reads and returns the current value of ITV. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of ITV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadItv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interval Timer Match Register (ITM).\r
+ \r
+ Reads and returns the current value of ITM.\r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of ITM.\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadItm (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
+ \r
+ Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to ITC.\r
+\r
+ @return The 64-bit value written to the ITC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteItc (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
+ \r
+ Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to ITM.\r
+\r
+ @return The 64-bit value written to the ITM.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteItm (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
+ \r
+ Writes the current value of ITV. The 64-bit value written to the ITV is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to ITV.\r
+\r
+ @return The 64-bit value written to the ITV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteItv (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Default Control Register (DCR).\r
+ \r
+ Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
+\r
+ @return The current value of DCR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadDcr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interruption Vector Address Register (IVA).\r
+ \r
+ Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
+\r
+ @return The current value of IVA.\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIva (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Page Table Address Register (PTA).\r
+ \r
+ Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
+\r
+ @return The current value of PTA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPta (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Default Control Register (DCR).\r
+ \r
+ Writes the current value of DCR. The 64-bit value written to the DCR is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to DCR.\r
+\r
+ @return The 64-bit value written to the DCR.\r