\r
@param String Pointer to a Null-terminated Unicode string.\r
\r
- @retval UINTN\r
+ @retval Value translated from String.\r
\r
**/\r
UINTN\r
\r
@param String Pointer to a Null-terminated Unicode string.\r
\r
- @retval UINT64\r
+ @retval Value translated from String.\r
\r
**/\r
UINT64\r
\r
@param String Pointer to a Null-terminated Unicode string.\r
\r
- @retval UINTN\r
+ @retval Value translated from String.\r
\r
**/\r
UINTN\r
\r
@param String Pointer to a Null-terminated Unicode string.\r
\r
- @retval UINT64\r
+ @retval Value translated from String.\r
\r
**/\r
UINT64\r
\r
@param String Pointer to a Null-terminated ASCII string.\r
\r
- @retval UINTN\r
+ @retval Value translated from String.\r
\r
**/\r
UINTN\r
\r
@param String Pointer to a Null-terminated ASCII string.\r
\r
- @retval UINT64\r
+ @retval Value translated from String.\r
\r
**/\r
UINT64\r
\r
@param String Pointer to a Null-terminated ASCII string.\r
\r
- @retval UINTN\r
+ @retval Value translated from String.\r
\r
**/\r
UINTN\r
\r
@param String Pointer to a Null-terminated ASCII string.\r
\r
- @retval UINT64\r
+ @retval Value translated from String.\r
\r
**/\r
UINT64\r
\r
@param FirstEntry A pointer to a node in a linked list.\r
@param SecondEntry A pointer to another node in the same linked list.\r
+ \r
+ @return SecondEntry\r
\r
**/\r
LIST_ENTRY *\r
\r
@param Buffer Pointer to a 24-bit value that may be unaligned.\r
\r
- @return The value read.\r
+ @return The value read from Buffer.\r
\r
**/\r
UINT32\r
@param Buffer Pointer to a 24-bit value that may be unaligned.\r
@param Value 24-bit value to write to Buffer.\r
\r
- @return The value written.\r
+ @return The value written to Buffer.\r
\r
**/\r
UINT32\r
\r
@param Uint32 Pointer to a 32-bit value that may be unaligned.\r
\r
- @return *Uint32\r
+ @return Value read from Uint32\r
\r
**/\r
UINT32\r
@param Uint32 Pointer to a 32-bit value that may be unaligned.\r
@param Value 32-bit value to write to Buffer.\r
\r
- @return Value\r
+ @return Value written to Uint32.\r
\r
**/\r
UINT32\r
\r
@param Uint64 Pointer to a 64-bit value that may be unaligned.\r
\r
- @return *Uint64\r
+ @return Value read from Uint64.\r
\r
**/\r
UINT64\r
@param Uint64 Pointer to a 64-bit value that may be unaligned.\r
@param Value 64-bit value to write to Buffer.\r
\r
- @return Value\r
+ @return Value written to Uint64.\r
\r
**/\r
UINT64\r
@param SpinLock A pointer to the spin lock to initialize to the released\r
state.\r
\r
- @return SpinLock\r
+ @return SpinLock in release state.\r
\r
**/\r
SPIN_LOCK *\r
\r
@param SpinLock A pointer to the spin lock to place in the acquired state.\r
\r
- @return SpinLock\r
+ @return SpinLock accquired lock.\r
\r
**/\r
SPIN_LOCK *\r
\r
@param SpinLock A pointer to the spin lock to release.\r
\r
- @return SpinLock\r
+ @return SpinLock released lock.\r
\r
**/\r
SPIN_LOCK *\r
@param CompareValue Pointer value used in compare operation.\r
@param ExchangeValue Pointer value used in exchange operation.\r
\r
+ @return The original *Value before exchange.\r
**/\r
VOID *\r
EFIAPI\r
/**\r
Enables CPU interrupts.\r
\r
- Enables CPU interrupts.\r
-\r
**/\r
VOID\r
EFIAPI\r
/**\r
Disables CPU interrupts.\r
\r
- Disables CPU interrupts.\r
-\r
**/\r
VOID\r
EFIAPI\r
Disables CPU interrupts and returns the interrupt state prior to the disable\r
operation.\r
\r
- Disables CPU interrupts and returns the interrupt state prior to the disable\r
- operation.\r
-\r
@retval TRUE CPU interrupts were enabled on entry to this call.\r
@retval FALSE CPU interrupts were disabled on entry to this call.\r
\r
Enables CPU interrupts for the smallest window required to capture any\r
pending interrupts.\r
\r
- Enables CPU interrupts for the smallest window required to capture any\r
- pending interrupts.\r
-\r
**/\r
VOID\r
EFIAPI\r
/**\r
Retrieves the current CPU interrupt state.\r
\r
- Retrieves the current CPU interrupt state. Returns TRUE is interrupts are\r
- currently enabled. Otherwise returns FALSE.\r
+ Returns TRUE is interrupts are currently enabled. Otherwise\r
+ returns FALSE.\r
\r
@retval TRUE CPU interrupts are enabled.\r
@retval FALSE CPU interrupts are disabled.\r