\r
#if defined (MDE_CPU_X64)\r
///\r
-/// X64 context buffer used by SetJump() and LongJump()\r
+/// x64 context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 Rbx;\r
Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 8-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 8-bit value is returned.\r
\r
If 8-bit operations are not supported, then ASSERT().\r
Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 16-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 16-bit value is returned.\r
\r
If 16-bit operations are not supported, then ASSERT().\r
Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 32-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 32-bit value is returned.\r
\r
If 32-bit operations are not supported, then ASSERT().\r
Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 64-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 64-bit value is returned.\r
\r
If 64-bit operations are not supported, then ASSERT().\r
CpuDeadLoop (\r
VOID\r
);\r
-\r
#if defined (MDE_CPU_IPF)\r
\r
/**\r
Flush a range of cache lines in the cache coherency domain of the calling\r
CPU.\r
\r
- Invalidates the cache lines specified by Address and Length. If Address is\r
- not aligned on a cache line boundary, then entire cache line containing\r
- Address is invalidated. If Address + Length is not aligned on a cache line\r
- boundary, then the entire instruction cache line containing Address + Length\r
- -1 is invalidated. This function may choose to invalidate the entire\r
- instruction cache if that is more efficient than invalidating the specified\r
- range. If Length is 0, the no instruction cache lines are invalidated.\r
- Address is returned.\r
+ Flushes the cache lines specified by Address and Length. If Address is not aligned \r
+ on a cache line boundary, then entire cache line containing Address is flushed. \r
+ If Address + Length is not aligned on a cache line boundary, then the entire cache \r
+ line containing Address + Length - 1 is flushed. This function may choose to flush \r
+ the entire cache if that is more efficient than flushing the specified range. If \r
+ Length is 0, the no cache lines are flushed. Address is returned. \r
+ This function is only available on IPF.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
\r
@param Length The number of bytes to invalidate from the instruction cache.\r
\r
- @return Address\r
+ @return Address.\r
\r
**/\r
VOID *\r
EFIAPI\r
-IpfFlushCacheRange (\r
+AsmFlushCacheRange (\r
IN VOID *Address,\r
IN UINTN Length\r
);\r
\r
#elif defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
-/// IA32 and X64 Specific Functions\r
+/// IA32 and x64 Specific Functions\r
/// Byte packed structure for 16-bit Real Mode EFLAGS\r
///\r
typedef union {\r
///\r
/// Byte packed structure for EFLAGS/RFLAGS\r
/// 32-bits on IA-32\r
-/// 64-bits on X64. The upper 32-bits on X64 are reserved\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved\r
///\r
typedef union {\r
struct {\r
///\r
/// Byte packed structure for Control Register 0 (CR0)\r
/// 32-bits on IA-32\r
-/// 64-bits on X64. The upper 32-bits on X64 are reserved\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved\r
///\r
typedef union {\r
struct {\r
///\r
/// Byte packed structure for Control Register 4 (CR4)\r
/// 32-bits on IA-32\r
-/// 64-bits on X64. The upper 32-bits on X64 are reserved\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved\r
///\r
typedef union {\r
struct {\r
\r
///\r
/// Byte packed structure for an IDTR, GDTR, LDTR descriptor\r
-/// @todo How to make this structure byte-packed in a compiler independent way?\r
///\r
#pragma pack (1)\r
typedef struct {\r
If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r
If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r
If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r
- This function is only available on IA-32 and X64.\r
+ This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit value to load into EAX prior to invoking the CPUID\r
instruction.\r
No parameter checking is performed on Index, and some Index values may cause\r
CPU exceptions. The caller must either guarantee that Index is valid, or the\r
caller must set up exception handlers to catch the exceptions. This function\r
- is only available on IA-32 and X64.\r
+ is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to read.\r
\r
the MSR is returned. No parameter checking is performed on Index or Value,\r
and some of these may cause CPU exceptions. The caller must either guarantee\r
that Index and Value are valid, or the caller must establish proper exception\r
- handlers. This function is only available on IA-32 and X64.\r
+ handlers. This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param Value The 32-bit value to write to the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise inclusive OR on the lower 32-bits, and\r
+ Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and\r
writes the result back to the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the lower 32-bits of the read result and the value specified by\r
OrData, and writes the result to the 64-bit MSR specified by Index. The lower\r
32-bits of the value written to the MSR is returned. No parameter checking is\r
performed on Index or OrData, and some of these may cause CPU exceptions. The\r
caller must either guarantee that Index and OrData are valid, or the caller\r
must establish proper exception handlers. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param OrData The value to OR with the read value from the MSR.\r
on Index or AndData, and some of these may cause CPU exceptions. The caller\r
must either guarantee that Index and AndData are valid, or the caller must\r
establish proper exception handlers. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive OR\r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR\r
on the lower 32-bits, and writes the result back to the 64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
lower 32-bits of the read result and the value specified by AndData\r
- preserving the upper 32-bits, performs a bitwise inclusive OR between the\r
+ preserving the upper 32-bits, performs a bitwise OR between the\r
result of the AND operation and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Address. The lower 32-bits of the value\r
written to the MSR is returned. No parameter checking is performed on Index,\r
AndData, or OrData, and some of these may cause CPU exceptions. The caller\r
must either guarantee that Index, AndData, and OrData are valid, or the\r
caller must establish proper exception handlers. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
specified by the StartBit and the EndBit. The value of the bit field is\r
returned. The caller must either guarantee that Index is valid, or the caller\r
must set up exception handlers to catch the exceptions. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
field is specified by the StartBit and the EndBit. All other bits in the\r
destination MSR are preserved. The lower 32-bits of the MSR written is\r
- returned. Extra left bits in Value are stripped. The caller must either\r
- guarantee that Index and the data written is valid, or the caller must set up\r
- exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ returned. The caller must either guarantee that Index and the data written \r
+ is valid, or the caller must set up exception handlers to catch the exceptions. \r
+ This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the\r
result back to the bit field in the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the read result and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Index. The lower 32-bits of the value\r
written to the MSR are returned. Extra left bits in OrData are stripped. The\r
caller must either guarantee that Index and the data written is valid, or\r
the caller must set up exception handlers to catch the exceptions. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
MSR are returned. Extra left bits in AndData are stripped. The caller must\r
either guarantee that Index and the data written is valid, or the caller must\r
set up exception handlers to catch the exceptions. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
AndData, and writes the result to the 64-bit MSR specified by Index. The\r
lower 32-bits of the value written to the MSR are returned. Extra left bits\r
in both AndData and OrData are stripped. The caller must either guarantee\r
that Index and the data written is valid, or the caller must set up exception\r
handlers to catch the exceptions. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
performed on Index, and some Index values may cause CPU exceptions. The\r
caller must either guarantee that Index is valid, or the caller must set up\r
exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to read.\r
\r
performed on Index or Value, and some of these may cause CPU exceptions. The\r
caller must either guarantee that Index and Value are valid, or the caller\r
must establish proper exception handlers. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param Value The 64-bit value to write to the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise inclusive OR, and writes the result\r
+ Reads a 64-bit MSR, performs a bitwise OR, and writes the result\r
back to the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the read result and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Index. The value written to the MSR is\r
returned. No parameter checking is performed on Index or OrData, and some of\r
these may cause CPU exceptions. The caller must either guarantee that Index\r
and OrData are valid, or the caller must establish proper exception handlers.\r
- This function is only available on IA-32 and X64.\r
+ This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param OrData The value to OR with the read value from the MSR.\r
parameter checking is performed on Index or OrData, and some of these may\r
cause CPU exceptions. The caller must either guarantee that Index and OrData\r
are valid, or the caller must establish proper exception handlers. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive\r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise \r
OR, and writes the result back to the 64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND between read\r
- result and the value specified by AndData, performs a bitwise inclusive OR\r
+ result and the value specified by AndData, performs a bitwise OR\r
between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 64-bit MSR specified by Index. The value written\r
to the MSR is returned. No parameter checking is performed on Index, AndData,\r
or OrData, and some of these may cause CPU exceptions. The caller must either\r
guarantee that Index, AndData, and OrData are valid, or the caller must\r
establish proper exception handlers. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
StartBit and the EndBit. The value of the bit field is returned. The caller\r
must either guarantee that Index is valid, or the caller must set up\r
exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
\r
Writes Value to a bit field in a 64-bit MSR. The bit field is specified by\r
the StartBit and the EndBit. All other bits in the destination MSR are\r
- preserved. The MSR written is returned. Extra left bits in Value are\r
- stripped. The caller must either guarantee that Index and the data written is\r
- valid, or the caller must set up exception handlers to catch the exceptions.\r
- This function is only available on IA-32 and X64.\r
+ preserved. The MSR written is returned. The caller must either guarantee \r
+ that Index and the data written is valid, or the caller must set up exception \r
+ handlers to catch the exceptions. This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
\r
\r
/**\r
- Reads a bit field in a 64-bit MSR, performs a bitwise inclusive OR, and\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and\r
writes the result back to the bit field in the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the read result and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Index. The value written to the MSR is\r
returned. Extra left bits in OrData are stripped. The caller must either\r
guarantee that Index and the data written is valid, or the caller must set up\r
exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
Extra left bits in AndData are stripped. The caller must either guarantee\r
that Index and the data written is valid, or the caller must set up exception\r
handlers to catch the exceptions. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by\r
- a bitwise inclusive OR between the read result and the value specified by\r
+ a bitwise OR between the read result and the value specified by\r
AndData, and writes the result to the 64-bit MSR specified by Index. The\r
value written to the MSR is returned. Extra left bits in both AndData and\r
OrData are stripped. The caller must either guarantee that Index and the data\r
written is valid, or the caller must set up exception handlers to catch the\r
- exceptions. This function is only available on IA-32 and X64.\r
+ exceptions. This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
Reads the current value of the EFLAGS register.\r
\r
Reads and returns the current value of the EFLAGS register. This function is\r
- only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a\r
- 64-bit value on X64.\r
+ only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a\r
+ 64-bit value on x64.\r
\r
- @return EFLAGS on IA-32 or RFLAGS on X64.\r
+ @return EFLAGS on IA-32 or RFLAGS on x64.\r
\r
**/\r
UINTN\r
Reads the current value of the Control Register 0 (CR0).\r
\r
Reads and returns the current value of CR0. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 0 (CR0).\r
\r
Reads the current value of the Control Register 2 (CR2).\r
\r
Reads and returns the current value of CR2. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 2 (CR2).\r
\r
Reads the current value of the Control Register 3 (CR3).\r
\r
Reads and returns the current value of CR3. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 3 (CR3).\r
\r
Reads the current value of the Control Register 4 (CR4).\r
\r
Reads and returns the current value of CR4. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 4 (CR4).\r
\r
Writes a value to Control Register 0 (CR0).\r
\r
Writes and returns a new value to CR0. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr0 The value to write to CR0.\r
\r
Writes a value to Control Register 2 (CR2).\r
\r
Writes and returns a new value to CR2. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr2 The value to write to CR2.\r
\r
Writes a value to Control Register 3 (CR3).\r
\r
Writes and returns a new value to CR3. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr3 The value to write to CR3.\r
\r
Writes a value to Control Register 4 (CR4).\r
\r
Writes and returns a new value to CR4. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr4 The value to write to CR4.\r
\r
Reads the current value of Debug Register 0 (DR0).\r
\r
Reads and returns the current value of DR0. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 0 (DR0).\r
\r
Reads the current value of Debug Register 1 (DR1).\r
\r
Reads and returns the current value of DR1. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 1 (DR1).\r
\r
Reads the current value of Debug Register 2 (DR2).\r
\r
Reads and returns the current value of DR2. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 2 (DR2).\r
\r
Reads the current value of Debug Register 3 (DR3).\r
\r
Reads and returns the current value of DR3. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 3 (DR3).\r
\r
Reads the current value of Debug Register 4 (DR4).\r
\r
Reads and returns the current value of DR4. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 4 (DR4).\r
\r
Reads the current value of Debug Register 5 (DR5).\r
\r
Reads and returns the current value of DR5. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 5 (DR5).\r
\r
Reads the current value of Debug Register 6 (DR6).\r
\r
Reads and returns the current value of DR6. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 6 (DR6).\r
\r
Reads the current value of Debug Register 7 (DR7).\r
\r
Reads and returns the current value of DR7. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 7 (DR7).\r
\r
Writes a value to Debug Register 0 (DR0).\r
\r
Writes and returns a new value to DR0. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr0 The value to write to Dr0.\r
\r
Writes a value to Debug Register 1 (DR1).\r
\r
Writes and returns a new value to DR1. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr1 The value to write to Dr1.\r
\r
Writes a value to Debug Register 2 (DR2).\r
\r
Writes and returns a new value to DR2. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr2 The value to write to Dr2.\r
\r
Writes a value to Debug Register 3 (DR3).\r
\r
Writes and returns a new value to DR3. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr3 The value to write to Dr3.\r
\r
Writes a value to Debug Register 4 (DR4).\r
\r
Writes and returns a new value to DR4. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr4 The value to write to Dr4.\r
\r
Writes a value to Debug Register 5 (DR5).\r
\r
Writes and returns a new value to DR5. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr5 The value to write to Dr5.\r
\r
Writes a value to Debug Register 6 (DR6).\r
\r
Writes and returns a new value to DR6. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr6 The value to write to Dr6.\r
\r
Writes a value to Debug Register 7 (DR7).\r
\r
Writes and returns a new value to DR7. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr7 The value to write to Dr7.\r
\r
Reads the current value of Code Segment Register (CS).\r
\r
Reads and returns the current value of CS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of CS.\r
\r
Reads the current value of Data Segment Register (DS).\r
\r
Reads and returns the current value of DS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of DS.\r
\r
Reads the current value of Extra Segment Register (ES).\r
\r
Reads and returns the current value of ES. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of ES.\r
\r
Reads the current value of FS Data Segment Register (FS).\r
\r
Reads and returns the current value of FS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of FS.\r
\r
Reads the current value of GS Data Segment Register (GS).\r
\r
Reads and returns the current value of GS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of GS.\r
\r
Reads the current value of Stack Segment Register (SS).\r
\r
Reads and returns the current value of SS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of SS.\r
\r
Reads the current value of Task Register (TR).\r
\r
Reads and returns the current value of TR. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of TR.\r
\r
Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
\r
Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
If Gdtr is NULL, then ASSERT().\r
\r
Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
\r
Writes and the current GDTR descriptor specified by Gdtr. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
If Gdtr is NULL, then ASSERT().\r
\r
Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
\r
Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
If Idtr is NULL, then ASSERT().\r
\r
Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
\r
Writes the current IDTR descriptor and returns it in Idtr. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
If Idtr is NULL, then ASSERT().\r
\r
Reads the current Local Descriptor Table Register(LDTR) selector.\r
\r
Reads and returns the current 16-bit LDTR descriptor value. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
@return The current selector of LDT.\r
\r
Writes the current Local Descriptor Table Register (LDTR) selector.\r
\r
Writes and the current LDTR descriptor specified by Ldtr. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
@param Ldtr 16-bit LDTR selector value.\r
\r
\r
Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
If Buffer is NULL, then ASSERT().\r
If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
Restores the current floating point/SSE/SSE2 state from the buffer specified\r
by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
If Buffer is NULL, then ASSERT().\r
If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r
Reads the current value of 64-bit MMX Register #0 (MM0).\r
\r
Reads and returns the current value of MM0. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM0.\r
\r
Reads the current value of 64-bit MMX Register #1 (MM1).\r
\r
Reads and returns the current value of MM1. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM1.\r
\r
Reads the current value of 64-bit MMX Register #2 (MM2).\r
\r
Reads and returns the current value of MM2. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM2.\r
\r
Reads the current value of 64-bit MMX Register #3 (MM3).\r
\r
Reads and returns the current value of MM3. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM3.\r
\r
Reads the current value of 64-bit MMX Register #4 (MM4).\r
\r
Reads and returns the current value of MM4. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM4.\r
\r
Reads the current value of 64-bit MMX Register #5 (MM5).\r
\r
Reads and returns the current value of MM5. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM5.\r
\r
Reads the current value of 64-bit MMX Register #6 (MM6).\r
\r
Reads and returns the current value of MM6. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM6.\r
\r
Reads the current value of 64-bit MMX Register #7 (MM7).\r
\r
Reads and returns the current value of MM7. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM7.\r
\r
Writes the current value of 64-bit MMX Register #0 (MM0).\r
\r
Writes the current value of MM0. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM0.\r
\r
Writes the current value of 64-bit MMX Register #1 (MM1).\r
\r
Writes the current value of MM1. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM1.\r
\r
Writes the current value of 64-bit MMX Register #2 (MM2).\r
\r
Writes the current value of MM2. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM2.\r
\r
Writes the current value of 64-bit MMX Register #3 (MM3).\r
\r
Writes the current value of MM3. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM3.\r
\r
Writes the current value of 64-bit MMX Register #4 (MM4).\r
\r
Writes the current value of MM4. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM4.\r
\r
Writes the current value of 64-bit MMX Register #5 (MM5).\r
\r
Writes the current value of MM5. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM5.\r
\r
Writes the current value of 64-bit MMX Register #6 (MM6).\r
\r
Writes the current value of MM6. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM6.\r
\r
Writes the current value of 64-bit MMX Register #7 (MM7).\r
\r
Writes the current value of MM7. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM7.\r
\r
Reads the current value of Time Stamp Counter (TSC).\r
\r
Reads and returns the current value of TSC. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of TSC\r
\r
Reads the current value of a Performance Counter (PMC).\r
\r
Reads and returns the current value of performance counter specified by\r
- Index. This function is only available on IA-32 and X64.\r
+ Index. This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit Performance Counter index to read.\r
\r
Sets up a monitor buffer that is used by AsmMwait().\r
\r
Executes a MONITOR instruction with the register state specified by Eax, Ecx\r
- and Edx. Returns Eax. This function is only available on IA-32 and X64.\r
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.\r
\r
@param Eax The value to load into EAX or RAX before executing the MONITOR\r
instruction.\r
Executes an MWAIT instruction.\r
\r
Executes an MWAIT instruction with the register state specified by Eax and\r
- Ecx. Returns Eax. This function is only available on IA-32 and X64.\r
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.\r
\r
@param Eax The value to load into EAX or RAX before executing the MONITOR\r
instruction.\r
Executes a WBINVD instruction.\r
\r
Executes a WBINVD instruction. This function is only available on IA-32 and\r
- X64.\r
+ x64.\r
\r
**/\r
VOID\r
Executes a INVD instruction.\r
\r
Executes a INVD instruction. This function is only available on IA-32 and\r
- X64.\r
+ x64.\r
\r
**/\r
VOID\r
coherency domain of the CPU.\r
\r
Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
- This function is only available on IA-32 and X64.\r
+ This function is only available on IA-32 and x64.\r
\r
@param LinearAddress The address of the cache line to flush. If the CPU is\r
in a physical addressing mode, then LinearAddress is a\r
\r
Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r
mode. This function assumes the current execution mode is 64-paging mode.\r
- This function is only available on X64. After the 64-bit paging mode is\r
+ This function is only available on x64. After the 64-bit paging mode is\r
disabled, control is transferred to the function specified by EntryPoint\r
using the new stack specified by NewStack and passing in the parameters\r
specified by Context1 and Context2. Context1 and Context2 are optional and\r
projects / mirror_edk2.git / blobdiff