/** @file\r
Provides string functions, linked list functions, math functions, synchronization\r
- functions, and CPU architecture specific functions.\r
+ functions, and CPU architecture-specific functions.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define __BASE_LIB__\r
\r
//\r
-// Definitions for architecture specific types\r
+// Definitions for architecture-specific types\r
//\r
#if defined (MDE_CPU_IA32)\r
///\r
-/// IA32 context buffer used by SetJump() and LongJump()\r
+/// IA-32 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT32 Ebx;\r
#if defined (MDE_CPU_IPF)\r
\r
///\r
-/// IPF context buffer used by SetJump() and LongJump()\r
+/// Itanium architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 F2[2];\r
\r
#if defined (MDE_CPU_X64)\r
///\r
-/// x64 context buffer used by SetJump() and LongJump()\r
+/// x64 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 Rbx;\r
UINT64 R14;\r
UINT64 R15;\r
UINT64 Rip;\r
+ UINT64 MxCsr;\r
+ UINT8 XmmBuffer[160]; ///< XMM6-XMM15\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
#endif // defined (MDE_CPU_EBC)\r
\r
+#if defined (MDE_CPU_ARM)\r
+\r
+typedef struct {\r
+ UINT32 R3; ///< Copy of R13\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 R14;\r
+} BASE_LIBRARY_JUMP_BUFFER;\r
+\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
+\r
+#endif // defined (MDE_CPU_ARM)\r
+\r
//\r
// String Services\r
//\r
InitializeListHead(), then ASSERT().\r
If PcdMaximumLinkedListLenth is not zero, and List contains more than\r
PcdMaximumLinkedListLenth nodes, then ASSERT().\r
- If Node is not a node in List, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
\r
@param List A pointer to the head node of a doubly linked list.\r
@param Node A pointer to a node in the doubly linked list.\r
\r
- @return Pointer to the next node if one exists. Otherwise a null value which\r
- is actually List is returned.\r
+ @return Pointer to the next node if one exists. Otherwise List is returned.\r
\r
**/\r
LIST_ENTRY *\r
IN CONST LIST_ENTRY *Node\r
);\r
\r
+ \r
+/**\r
+ Retrieves the previous node of a doubly linked list.\r
+ \r
+ Returns the node of a doubly linked list that precedes Node. \r
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()\r
+ or InitializeListHead(). If List is empty, then List is returned.\r
+ \r
+ If List is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT().\r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and List contains more than\r
+ PcdMaximumLinkedListLenth nodes, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
+ \r
+ @param List A pointer to the head node of a doubly linked list.\r
+ @param Node A pointer to a node in the doubly linked list.\r
+ \r
+ @return Pointer to the previous node if one exists. Otherwise List is returned.\r
+ \r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+GetPreviousNode (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
+ );\r
\r
+ \r
/**\r
Checks to see if a doubly linked list is empty or not.\r
\r
If PcdMaximumLinkedListLenth is not zero, and the number of nodes\r
in List, including the List node, is greater than or equal to\r
PcdMaximumLinkedListLength, then ASSERT().\r
- If Node is not a node in List and Node is not equal to List, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal \r
+ to List, then ASSERT().\r
\r
@param List A pointer to the head node of a doubly linked list.\r
@param Node A pointer to a node in the doubly linked list.\r
If PcdMaximumLinkedListLenth is not zero, and the number of nodes\r
in List, including the List node, is greater than or equal to\r
PcdMaximumLinkedListLength, then ASSERT().\r
- If Node is not a node in List, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
\r
@param List A pointer to the head node of a doubly linked list.\r
@param Node A pointer to a node in the doubly linked list.\r
\r
If FirstEntry is NULL, then ASSERT().\r
If SecondEntry is NULL, then ASSERT().\r
- If SecondEntry and FirstEntry are not in the same linked list, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the \r
+ same linked list, then ASSERT().\r
If PcdMaximumLinkedListLength is not zero, and the number of nodes in the\r
linked list containing the FirstEntry and SecondEntry nodes, including\r
the FirstEntry and SecondEntry nodes, is greater than or equal to\r
calls to LongJump() cause a non-zero value to be returned by SetJump().\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.\r
The same structure must never be used for more than one CPU architecture context.\r
the state of JumpBuffer.\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
If Value is 0, then ASSERT().\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
by Context1 and Context2. Context1 and Context2 are optional and may\r
be NULL. The function EntryPoint must never return. This function\r
supports a variable number of arguments following the NewStack parameter.\r
- These additional arguments are ignored on IA-32, x64, and EBC.\r
- IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.\r
+ Itanium processors expect one additional parameter of type VOID * that specifies\r
the new backing store pointer.\r
\r
If EntryPoint is NULL, then ASSERT().\r
function.\r
@param NewStack A pointer to the new stack to use for the EntryPoint\r
function.\r
- @param ... This variable argument list is ignored for IA32, x64, and EBC. \r
- For IPF, this variable argument list is expected to contain \r
+ @param ... This variable argument list is ignored for IA-32, x64, and EBC architectures. \r
+ For Itanium processors, this variable argument list is expected to contain \r
a single parameter of type VOID * that specifies the new backing \r
store pointer.\r
\r
line containing Address + Length - 1 is flushed. This function may choose to flush \r
the entire cache if that is more efficient than flushing the specified range. If \r
Length is 0, the no cache lines are flushed. Address is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
Executes a FC instruction\r
Executes a FC instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
Executes a FC.I instruction.\r
Executes a FC.I instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
No parameter checking is performed on Index. If the Index value is beyond the\r
implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on IPF.\r
+ catch the faults. This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Processor Identifier Register index to read.\r
\r
\r
/**\r
Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of PSR.\r
\r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on IPF.\r
+ fault handlers to catch the faults. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PSR.\r
\r
Reads the current value of 64-bit Kernel Register #0 (KR0).\r
\r
Reads and returns the current value of KR0. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR0.\r
\r
Reads the current value of 64-bit Kernel Register #1 (KR1).\r
\r
Reads and returns the current value of KR1. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR1.\r
\r
Reads the current value of 64-bit Kernel Register #2 (KR2).\r
\r
Reads and returns the current value of KR2. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR2.\r
\r
Reads the current value of 64-bit Kernel Register #3 (KR3).\r
\r
Reads and returns the current value of KR3. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR3.\r
\r
Reads the current value of 64-bit Kernel Register #4 (KR4).\r
\r
Reads and returns the current value of KR4. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR4.\r
\r
Reads the current value of 64-bit Kernel Register #5 (KR5).\r
\r
Reads and returns the current value of KR5. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR5.\r
\r
Reads the current value of 64-bit Kernel Register #6 (KR6).\r
\r
Reads and returns the current value of KR6. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR6.\r
\r
Reads the current value of 64-bit Kernel Register #7 (KR7).\r
\r
Reads and returns the current value of KR7. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR7.\r
\r
Write the current value of 64-bit Kernel Register #0 (KR0).\r
\r
Writes the current value of KR0. The 64-bit value written to \r
- the KR0 is returned. This function is only available on IPF.\r
+ the KR0 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR0.\r
\r
Write the current value of 64-bit Kernel Register #1 (KR1).\r
\r
Writes the current value of KR1. The 64-bit value written to \r
- the KR1 is returned. This function is only available on IPF.\r
+ the KR1 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR1.\r
\r
Write the current value of 64-bit Kernel Register #2 (KR2).\r
\r
Writes the current value of KR2. The 64-bit value written to \r
- the KR2 is returned. This function is only available on IPF.\r
+ the KR2 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR2.\r
\r
Write the current value of 64-bit Kernel Register #3 (KR3).\r
\r
Writes the current value of KR3. The 64-bit value written to \r
- the KR3 is returned. This function is only available on IPF.\r
+ the KR3 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR3.\r
\r
Write the current value of 64-bit Kernel Register #4 (KR4).\r
\r
Writes the current value of KR4. The 64-bit value written to \r
- the KR4 is returned. This function is only available on IPF.\r
+ the KR4 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR4.\r
\r
Write the current value of 64-bit Kernel Register #5 (KR5).\r
\r
Writes the current value of KR5. The 64-bit value written to \r
- the KR5 is returned. This function is only available on IPF.\r
+ the KR5 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR5.\r
\r
Write the current value of 64-bit Kernel Register #6 (KR6).\r
\r
Writes the current value of KR6. The 64-bit value written to \r
- the KR6 is returned. This function is only available on IPF.\r
+ the KR6 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR6.\r
\r
Write the current value of 64-bit Kernel Register #7 (KR7).\r
\r
Writes the current value of KR7. The 64-bit value written to \r
- the KR7 is returned. This function is only available on IPF.\r
+ the KR7 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR7.\r
\r
Reads the current value of Interval Timer Counter Register (ITC).\r
\r
Reads and returns the current value of ITC.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITC.\r
\r
Reads the current value of Interval Timer Vector Register (ITV).\r
\r
Reads and returns the current value of ITV. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITV.\r
\r
Reads the current value of Interval Timer Match Register (ITM).\r
\r
Reads and returns the current value of ITM.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITM.\r
**/\r
Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
\r
Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITC.\r
\r
Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
\r
Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITM.\r
\r
reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITV.\r
\r
/**\r
Reads the current value of Default Control Register (DCR).\r
\r
- Reads and returns the current value of DCR. This function is only available on IPF.\r
+ Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
\r
@return The current value of DCR.\r
\r
/**\r
Reads the current value of Interruption Vector Address Register (IVA).\r
\r
- Reads and returns the current value of IVA. This function is only available on IPF.\r
+ Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
\r
@return The current value of IVA.\r
**/\r
/**\r
Reads the current value of Page Table Address Register (PTA).\r
\r
- Reads and returns the current value of PTA. This function is only available on IPF.\r
+ Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
\r
@return The current value of PTA.\r
\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to DCR.\r
\r
Writes the current value of IVA. The 64-bit value written to the IVA is returned. \r
The size of vector table is 32 K bytes and is 32 K bytes aligned\r
the low 15 bits of Value is ignored when written.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to IVA.\r
\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PTA.\r
\r
/**\r
Reads the current value of Local Interrupt ID Register (LID).\r
\r
- Reads and returns the current value of LID. This function is only available on IPF.\r
+ Reads and returns the current value of LID. This function is only available on Itanium processors.\r
\r
@return The current value of LID.\r
\r
/**\r
Reads the current value of External Interrupt Vector Register (IVR).\r
\r
- Reads and returns the current value of IVR. This function is only available on IPF. \r
+ Reads and returns the current value of IVR. This function is only available on Itanium processors. \r
\r
@return The current value of IVR.\r
\r
/**\r
Reads the current value of Task Priority Register (TPR).\r
\r
- Reads and returns the current value of TPR. This function is only available on IPF. \r
+ Reads and returns the current value of TPR. This function is only available on Itanium processors. \r
\r
@return The current value of TPR.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #0 (IRR0).\r
\r
- Reads and returns the current value of IRR0. This function is only available on IPF. \r
+ Reads and returns the current value of IRR0. This function is only available on Itanium processors. \r
\r
@return The current value of IRR0.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #1 (IRR1).\r
\r
- Reads and returns the current value of IRR1. This function is only available on IPF. \r
+ Reads and returns the current value of IRR1. This function is only available on Itanium processors. \r
\r
@return The current value of IRR1.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #2 (IRR2).\r
\r
- Reads and returns the current value of IRR2. This function is only available on IPF.\r
+ Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
\r
@return The current value of IRR2.\r
\r
/**\r
Reads the current value of External Interrupt Request Register #3 (IRR3).\r
\r
- Reads and returns the current value of IRR3. This function is only available on IPF. \r
+ Reads and returns the current value of IRR3. This function is only available on Itanium processors. \r
\r
@return The current value of IRR3.\r
\r
/**\r
Reads the current value of Performance Monitor Vector Register (PMV).\r
\r
- Reads and returns the current value of PMV. This function is only available on IPF. \r
+ Reads and returns the current value of PMV. This function is only available on Itanium processors. \r
\r
@return The current value of PMV.\r
\r
/**\r
Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
\r
- Reads and returns the current value of CMCV. This function is only available on IPF.\r
+ Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
\r
@return The current value of CMCV.\r
\r
/**\r
Reads the current value of Local Redirection Register #0 (LRR0).\r
\r
- Reads and returns the current value of LRR0. This function is only available on IPF. \r
+ Reads and returns the current value of LRR0. This function is only available on Itanium processors. \r
\r
@return The current value of LRR0.\r
\r
/**\r
Reads the current value of Local Redirection Register #1 (LRR1).\r
\r
- Reads and returns the current value of LRR1. This function is only available on IPF.\r
+ Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
\r
@return The current value of LRR1.\r
\r
reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LID.\r
\r
reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to TPR.\r
\r
/**\r
Performs a write operation on End OF External Interrupt Register (EOI).\r
\r
- Writes a value of 0 to the EOI Register. This function is only available on IPF.\r
+ Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
\r
**/\r
VOID\r
to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PMV.\r
\r
to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to CMCV.\r
\r
to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR0.\r
\r
to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR1.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to read.\r
\r
the implemented DBR register range, a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Index is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to read.\r
\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMC register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to read.\r
\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMD register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to read.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to write.\r
@param Value The 64-bit value to write to IBR.\r
DBR register range, a Reserved Register/Field fault may occur. The caller must\r
either guarantee that Index is valid, or the caller must set up fault handlers to\r
catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to write.\r
@param Value The 64-bit value to write to DBR.\r
counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
dependent. No parameter checking is performed on Index. If the Index value is\r
beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to write.\r
@param Value The 64-bit value to write to PMC.\r
performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
is implementation dependent. No parameter checking is performed on Index. If the\r
Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to write.\r
@param Value The 64-bit value to write to PMD.\r
Reads the current value of 64-bit Global Pointer (GP).\r
\r
Reads and returns the current value of GP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of GP.\r
\r
\r
Writes the current value of GP. The 64-bit value written to the GP is returned.\r
No parameter checking is performed on Value.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to GP.\r
\r
Reads the current value of 64-bit Stack Pointer (SP).\r
\r
Reads and returns the current value of SP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of SP.\r
\r
\r
Reads and returns the control register specified by Index. The valid Index valued are defined\r
above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
\r
@param Index The index of the control register to read.\r
\r
\r
Reads and returns the application register specified by Index. The valid Index valued are defined\r
above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
\r
@param Index The index of the application register to read.\r
\r
parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on IPF.\r
+ only available on Itanium processors.\r
\r
@param Index The 8-bit Machine Specific Register index to read.\r
\r
parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on IPF.\r
+ only available on Itanium processors.\r
\r
@param Index The 8-bit Machine Specific Register index to write.\r
@param Value The 64-bit value to write to the Machine Specific Register.\r
If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
and -1 is returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@retval 1 The CPU is in virtual mode.\r
@retval 0 The CPU is in physical mode.\r
argument return value may be returned or undefined result may occur during the\r
execution of the procedure. If the PalEntryPoint does not point to a valid\r
PAL entry point then the system behavior is undefined. This function is only\r
- available on IPF.\r
+ available on Itanium processors.\r
\r
@param PalEntryPoint The PAL procedure calls entry point.\r
@param Index The PAL procedure Index number.\r
\r
#if defined (MDE_CPU_IA32)\r
///\r
-/// Byte packed structure for an IA32 Interrupt Gate Descriptor\r
+/// Byte packed structure for an IA-32 Interrupt Gate Descriptor\r
///\r
typedef union {\r
struct {\r
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