/** @file\r
Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.\r
- \r
- This library is identical to the PCI Library, except the access method for performing PCI \r
- configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows \r
- access to PCI Segment #0.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+ This library is identical to the PCI Library, except the access method for performing PCI\r
+ configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows\r
+ access to PCI Segment #0.\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __PCI_CF8_LIB_H__\r
#define __PCI_CF8_LIB_H__\r
\r
-\r
/**\r
Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r
address that can be passed to the PCI Library functions.\r
@return The encode PCI address.\r
\r
**/\r
-#define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r
+#define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset) \\r
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
/**\r
- Register a PCI device so PCI configuration registers may be accessed after \r
+ Registers a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
+\r
+ Registers the PCI device specified by Address so all the PCI configuration registers\r
+ associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
+\r
If Address > 0x0FFFFFFF, then ASSERT().\r
+ If the register specified by Address >= 0x100, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
UINT8\r
EFIAPI\r
PciCf8Read8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8Write8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with\r
an 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 8-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
UINT8\r
EFIAPI\r
PciCf8Or8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8And8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise inclusive OR with another 8-bit value.\r
+ value, followed a bitwise OR with another 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
+ performs a bitwise OR between the result of the AND operation and\r
the value specified by OrData, and writes the result to the 8-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
UINT8\r
EFIAPI\r
PciCf8AndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8BitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciCf8BitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
writes the result back to the bit field in the 8-bit port.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 8-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciCf8BitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciCf8BitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
8-bit port.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
+ bitwise AND followed by a bitwise OR between the read result and\r
the value specified by AndData, and writes the result to the 8-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciCf8BitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8Read16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8Write16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r
+ Performs a bitwise OR of a 16-bit PCI configuration register with\r
a 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 16-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
UINT16\r
EFIAPI\r
PciCf8Or16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8And16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise inclusive OR with another 16-bit value.\r
+ value, followed a bitwise OR with another 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
+ performs a bitwise OR between the result of the AND operation and\r
the value specified by OrData, and writes the result to the 16-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
UINT16\r
EFIAPI\r
PciCf8AndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8BitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciCf8BitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
writes the result back to the bit field in the 16-bit port.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 16-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciCf8BitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciCf8BitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
16-bit port.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
+ bitwise AND followed by a bitwise OR between the read result and\r
the value specified by AndData, and writes the result to the 16-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciCf8BitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8Read32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8Write32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with\r
a 32-bit value.\r
\r
Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 32-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
UINT32\r
EFIAPI\r
PciCf8Or32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8And32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise inclusive OR with another 32-bit value.\r
+ value, followed a bitwise OR with another 32-bit value.\r
\r
Reads the 32-bit PCI configuration register specified by Address, performs a\r
bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
+ performs a bitwise OR between the result of the AND operation and\r
the value specified by OrData, and writes the result to the 32-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
UINT32\r
EFIAPI\r
PciCf8AndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8BitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciCf8BitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
writes the result back to the bit field in the 32-bit port.\r
\r
Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 32-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciCf8BitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciCf8BitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
32-bit port.\r
\r
Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
+ bitwise AND followed by a bitwise OR between the read result and\r
the value specified by AndData, and writes the result to the 32-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciCf8BitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
Size into the buffer specified by Buffer. This function only allows the PCI\r
configuration registers from a single PCI function to be read. Size is\r
returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
UINTN\r
EFIAPI\r
PciCf8ReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
Size from the buffer specified by Buffer. This function only allows the PCI\r
configuration registers from a single PCI function to be written. Size is\r
returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
UINTN\r
EFIAPI\r
PciCf8WriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
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