UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdePkg / Include / Library / PciLib.h

diff --git a/MdePkg/Include/Library/PciLib.h b/MdePkg/Include/Library/PciLib.h
index 4d21cb77089c6cf8e0a753fb45725a718c9a61a7..382a3df5b2d6562b8a7863df225ce168e10255cb 100644 (file)
--- a/MdePkg/Include/Library/PciLib.h
+++ b/MdePkg/Include/Library/PciLib.h
@@ -1,16 +1,17 @@
 /** @file\r
 /** @file\r

-  PCI Library Services for PCI Segment #0\r
+  Provides services to access PCI Configuration Space.\r

 \r
 \r

-  Copyright (c) 2006, Intel Corporation\r
-  All rights reserved. This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
+  These functions perform PCI configuration cycles using the default PCI configuration\r
+  access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,\r
+  or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some\r
+  alternate access method.  Modules will typically use the PCI Library for its PCI configuration\r
+  accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or\r
+  PCI Express Library may be used in conjunction with the PCI Library.  The functionality of\r
+  these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use\r
+  explicit access methods.\r

 \r
 \r

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-  Module Name:  PciLib.h\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r

 \r
 **/\r
 \r
 \r
 **/\r
 \r


@@ -30,8 +31,35 @@
   @return The encoded PCI address.\r
 \r
 **/\r
   @return The encoded PCI address.\r
 \r
 **/\r

-#define PCI_LIB_ADDRESS(Bus,Device,Function,Offset)   \\r
-  (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
+#define PCI_LIB_ADDRESS(Bus, Device, Function, Register)   \\r
+  (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
+\r
+/**\r
+  Registers a PCI device so PCI configuration registers may be accessed after\r
+  SetVirtualAddressMap().\r
+\r
+  Registers the PCI device specified by Address so all the PCI configuration registers\r
+  associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
+\r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
+\r
+  @param  Address Address that encodes the PCI Bus, Device, Function and\r
+                  Register.\r
+\r
+  @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function\r
+                                   after ExitBootServices().\r
+  @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
+                                   at runtime could not be mapped.\r
+  @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to\r
+                                   complete the registration.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PciRegisterForRuntimeAccess (\r
+  IN UINTN  Address\r
+  );\r

 \r
 /**\r
   Reads an 8-bit PCI configuration register.\r
 \r
 /**\r
   Reads an 8-bit PCI configuration register.\r


@@ -51,7 +79,7 @@
 UINT8\r
 EFIAPI\r
 PciRead8 (\r
 UINT8\r
 EFIAPI\r
 PciRead8 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -73,16 +101,16 @@ PciRead8 (
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     Data\r
+  IN      UINTN  Address,\r
+  IN      UINT8  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r

-  Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r
+  Performs a bitwise OR of an 8-bit PCI configuration register with\r

   an 8-bit value.\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r
   an 8-bit value.\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r

-  bitwise inclusive OR between the read result and the value specified by\r
+  bitwise OR between the read result and the value specified by\r

   OrData, and writes the result to the 8-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r
   OrData, and writes the result to the 8-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r


@@ -100,8 +128,8 @@ PciWrite8 (
 UINT8\r
 EFIAPI\r
 PciOr8 (\r
 UINT8\r
 EFIAPI\r
 PciOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -127,17 +155,17 @@ PciOr8 (
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData\r

   );\r
 \r
 /**\r
   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
   );\r
 \r
 /**\r
   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r

-  value, followed a  bitwise inclusive OR with another 8-bit value.\r
+  value, followed by a bitwise OR with another 8-bit value.\r

 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r
   bitwise AND between the read result and the value specified by AndData,\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r
   bitwise AND between the read result and the value specified by AndData,\r

-  performs a bitwise inclusive OR between the result of the AND operation and\r
+  performs a bitwise OR between the result of the AND operation and\r

   the value specified by OrData, and writes the result to the 8-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r
   the value specified by OrData, and writes the result to the 8-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r


@@ -156,9 +184,9 @@ PciAnd8 (
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -185,9 +213,9 @@ PciAndThenOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -202,6 +230,7 @@ PciBitFieldRead8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -216,10 +245,10 @@ PciBitFieldRead8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -227,7 +256,7 @@ PciBitFieldWrite8 (
   writes the result back to the bit field in the 8-bit port.\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r
   writes the result back to the bit field in the 8-bit port.\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r

-  bitwise inclusive OR between the read result and the value specified by\r
+  bitwise OR between the read result and the value specified by\r

   OrData, and writes the result to the 8-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r
   OrData, and writes the result to the 8-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r


@@ -237,6 +266,7 @@ PciBitFieldWrite8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -251,10 +281,10 @@ PciBitFieldWrite8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -272,6 +302,7 @@ PciBitFieldOr8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -286,19 +317,19 @@ PciBitFieldOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData\r

   );\r
 \r
 /**\r
   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
   );\r
 \r
 /**\r
   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r

-  bitwise inclusive OR, and writes the result back to the bit field in the\r
+  bitwise OR, and writes the result back to the bit field in the\r

   8-bit port.\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r
   8-bit port.\r
 \r
   Reads the 8-bit PCI configuration register specified by Address, performs a\r

-  bitwise AND followed by a bitwise inclusive OR between the read result and\r
+  bitwise AND followed by a bitwise OR between the read result and\r

   the value specified by AndData, and writes the result to the 8-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r
   the value specified by AndData, and writes the result to the 8-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r


@@ -309,6 +340,8 @@ PciBitFieldAnd8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -324,11 +357,11 @@ PciBitFieldAnd8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -350,7 +383,7 @@ PciBitFieldAndThenOr8 (
 UINT16\r
 EFIAPI\r
 PciRead16 (\r
 UINT16\r
 EFIAPI\r
 PciRead16 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -373,16 +406,16 @@ PciRead16 (
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    Data\r
+  IN      UINTN   Address,\r
+  IN      UINT16  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r

-  Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r
+  Performs a bitwise OR of a 16-bit PCI configuration register with\r

   a 16-bit value.\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r
   a 16-bit value.\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r

-  bitwise inclusive OR between the read result and the value specified by\r
+  bitwise OR between the read result and the value specified by\r

   OrData, and writes the result to the 16-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r
   OrData, and writes the result to the 16-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r


@@ -401,8 +434,8 @@ PciWrite16 (
 UINT16\r
 EFIAPI\r
 PciOr16 (\r
 UINT16\r
 EFIAPI\r
 PciOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -429,17 +462,17 @@ PciOr16 (
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData\r

   );\r
 \r
 /**\r
   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
   );\r
 \r
 /**\r
   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r

-  value, followed a  bitwise inclusive OR with another 16-bit value.\r
+  value, followed a  bitwise OR with another 16-bit value.\r

 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r
   bitwise AND between the read result and the value specified by AndData,\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r
   bitwise AND between the read result and the value specified by AndData,\r

-  performs a bitwise inclusive OR between the result of the AND operation and\r
+  performs a bitwise OR between the result of the AND operation and\r

   the value specified by OrData, and writes the result to the 16-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r
   the value specified by OrData, and writes the result to the 16-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r


@@ -459,9 +492,9 @@ PciAnd16 (
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -489,9 +522,9 @@ PciAndThenOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -507,6 +540,7 @@ PciBitFieldRead16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -521,10 +555,10 @@ PciBitFieldRead16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -532,7 +566,7 @@ PciBitFieldWrite16 (
   writes the result back to the bit field in the 16-bit port.\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r
   writes the result back to the bit field in the 16-bit port.\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r

-  bitwise inclusive OR between the read result and the value specified by\r
+  bitwise OR between the read result and the value specified by\r

   OrData, and writes the result to the 16-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r
   OrData, and writes the result to the 16-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r


@@ -543,6 +577,7 @@ PciBitFieldWrite16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -557,10 +592,10 @@ PciBitFieldWrite16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -579,6 +614,7 @@ PciBitFieldOr16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -593,19 +629,19 @@ PciBitFieldOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData\r

   );\r
 \r
 /**\r
   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
   );\r
 \r
 /**\r
   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r

-  bitwise inclusive OR, and writes the result back to the bit field in the\r
+  bitwise OR, and writes the result back to the bit field in the\r

   16-bit port.\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r
   16-bit port.\r
 \r
   Reads the 16-bit PCI configuration register specified by Address, performs a\r

-  bitwise AND followed by a bitwise inclusive OR between the read result and\r
+  bitwise AND followed by a bitwise OR between the read result and\r

   the value specified by AndData, and writes the result to the 16-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r
   the value specified by AndData, and writes the result to the 16-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r


@@ -617,6 +653,8 @@ PciBitFieldAnd16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -632,11 +670,11 @@ PciBitFieldAnd16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -658,7 +696,7 @@ PciBitFieldAndThenOr16 (
 UINT32\r
 EFIAPI\r
 PciRead32 (\r
 UINT32\r
 EFIAPI\r
 PciRead32 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -681,16 +719,16 @@ PciRead32 (
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    Data\r
+  IN      UINTN   Address,\r
+  IN      UINT32  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r

-  Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r
+  Performs a bitwise OR of a 32-bit PCI configuration register with\r

   a 32-bit value.\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r
   a 32-bit value.\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r

-  bitwise inclusive OR between the read result and the value specified by\r
+  bitwise OR between the read result and the value specified by\r

   OrData, and writes the result to the 32-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r
   OrData, and writes the result to the 32-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r


@@ -709,8 +747,8 @@ PciWrite32 (
 UINT32\r
 EFIAPI\r
 PciOr32 (\r
 UINT32\r
 EFIAPI\r
 PciOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -737,17 +775,17 @@ PciOr32 (
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData\r

   );\r
 \r
 /**\r
   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
   );\r
 \r
 /**\r
   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r

-  value, followed a  bitwise inclusive OR with another 32-bit value.\r
+  value, followed a  bitwise OR with another 32-bit value.\r

 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r
   bitwise AND between the read result and the value specified by AndData,\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r
   bitwise AND between the read result and the value specified by AndData,\r

-  performs a bitwise inclusive OR between the result of the AND operation and\r
+  performs a bitwise OR between the result of the AND operation and\r

   the value specified by OrData, and writes the result to the 32-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r
   the value specified by OrData, and writes the result to the 32-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r


@@ -767,9 +805,9 @@ PciAnd32 (
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -797,9 +835,9 @@ PciAndThenOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -815,6 +853,7 @@ PciBitFieldRead32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -829,10 +868,10 @@ PciBitFieldRead32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -840,7 +879,7 @@ PciBitFieldWrite32 (
   writes the result back to the bit field in the 32-bit port.\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r
   writes the result back to the bit field in the 32-bit port.\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r

-  bitwise inclusive OR between the read result and the value specified by\r
+  bitwise OR between the read result and the value specified by\r

   OrData, and writes the result to the 32-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r
   OrData, and writes the result to the 32-bit PCI configuration register\r
   specified by Address. The value written to the PCI configuration register is\r
   returned. This function must guarantee that all PCI read and write operations\r


@@ -851,6 +890,7 @@ PciBitFieldWrite32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -865,10 +905,10 @@ PciBitFieldWrite32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -887,6 +927,7 @@ PciBitFieldOr32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -901,19 +942,19 @@ PciBitFieldOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData\r

   );\r
 \r
 /**\r
   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
   );\r
 \r
 /**\r
   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r

-  bitwise inclusive OR, and writes the result back to the bit field in the\r
+  bitwise OR, and writes the result back to the bit field in the\r

   32-bit port.\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r
   32-bit port.\r
 \r
   Reads the 32-bit PCI configuration register specified by Address, performs a\r

-  bitwise AND followed by a bitwise inclusive OR between the read result and\r
+  bitwise AND followed by a bitwise OR between the read result and\r

   the value specified by AndData, and writes the result to the 32-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r
   the value specified by AndData, and writes the result to the 32-bit PCI\r
   configuration register specified by Address. The value written to the PCI\r
   configuration register is returned. This function must guarantee that all PCI\r


@@ -925,6 +966,8 @@ PciBitFieldAnd32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -940,11 +983,11 @@ PciBitFieldAnd32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -954,14 +997,13 @@ PciBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r

-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r

   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
   If StartAddress > 0x0FFFFFFF, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
   If StartAddress > 0x0FFFFFFF, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r

-  If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().\r
-  If Buffer is NULL, then ASSERT().\r
+  If Size > 0 and Buffer is NULL, then ASSERT().\r

 \r
   @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                         Function and Register.\r
 \r
   @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                         Function and Register.\r


@@ -974,9 +1016,9 @@ PciBitFieldAndThenOr32 (
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r

-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  OUT     VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  OUT     VOID   *Buffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -987,29 +1029,28 @@ PciReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r

-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r

   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
   If StartAddress > 0x0FFFFFFF, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
   If StartAddress > 0x0FFFFFFF, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r

-  If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().\r
-  If Buffer is NULL, then ASSERT().\r
+  If Size > 0 and Buffer is NULL, then ASSERT().\r

 \r
   @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                         Function and Register.\r
   @param  Size          Size in bytes of the transfer.\r
   @param  Buffer        Pointer to a buffer containing the data to write.\r
 \r
 \r
   @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                         Function and Register.\r
   @param  Size          Size in bytes of the transfer.\r
   @param  Buffer        Pointer to a buffer containing the data to write.\r
 \r

-  @return Size\r
+  @return Size written to StartAddress.\r

 \r
 **/\r
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r
 \r
 **/\r
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r

-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  IN      VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  IN      VOID   *Buffer\r

   );\r
 \r
 #endif\r
   );\r
 \r
 #endif\r