UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdePkg / Include / Library / PciLib.h

diff --git a/MdePkg/Include/Library/PciLib.h b/MdePkg/Include/Library/PciLib.h
index a6f6de6a73383208494f524e8a68ca5ec69727ff..382a3df5b2d6562b8a7863df225ce168e10255cb 100644 (file)
--- a/MdePkg/Include/Library/PciLib.h
+++ b/MdePkg/Include/Library/PciLib.h
@@ -1,23 +1,17 @@
 /** @file\r
   Provides services to access PCI Configuration Space.\r
 /** @file\r
   Provides services to access PCI Configuration Space.\r

-  \r
-  These functions perform PCI configuration cycles using the default PCI configuration \r
-  access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, \r
-  or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some \r
-  alternate access method.  Modules will typically use the PCI Library for its PCI configuration \r
-  accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or \r
-  PCI Express Library may be used in conjunction with the PCI Library.  The functionality of \r
-  these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use \r
-  explicit access methods.\r

 \r
 \r

-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+  These functions perform PCI configuration cycles using the default PCI configuration\r
+  access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,\r
+  or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some\r
+  alternate access method.  Modules will typically use the PCI Library for its PCI configuration\r
+  accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or\r
+  PCI Express Library may be used in conjunction with the PCI Library.  The functionality of\r
+  these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use\r
+  explicit access methods.\r

 \r
 \r

-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r

 \r
 **/\r
 \r
 \r
 **/\r
 \r


@@ -37,23 +31,23 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @return The encoded PCI address.\r
 \r
 **/\r
   @return The encoded PCI address.\r
 \r
 **/\r

-#define PCI_LIB_ADDRESS(Bus,Device,Function,Register)   \\r
+#define PCI_LIB_ADDRESS(Bus, Device, Function, Register)   \\r

   (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
 \r
 /**\r
   (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
 \r
 /**\r

-  Registers a PCI device so PCI configuration registers may be accessed after \r
+  Registers a PCI device so PCI configuration registers may be accessed after\r

   SetVirtualAddressMap().\r
   SetVirtualAddressMap().\r

-  \r
-  Registers the PCI device specified by Address so all the PCI configuration registers \r
+\r
+  Registers the PCI device specified by Address so all the PCI configuration registers\r

   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r

-  \r
+\r

   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r

-  \r
+\r

   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r

-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function \r
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function\r

                                    after ExitBootServices().\r
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
                                    at runtime could not be mapped.\r
                                    after ExitBootServices().\r
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
                                    at runtime could not be mapped.\r


@@ -85,7 +79,7 @@ PciRegisterForRuntimeAccess (
 UINT8\r
 EFIAPI\r
 PciRead8 (\r
 UINT8\r
 EFIAPI\r
 PciRead8 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -107,8 +101,8 @@ PciRead8 (
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINT8  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -134,8 +128,8 @@ PciWrite8 (
 UINT8\r
 EFIAPI\r
 PciOr8 (\r
 UINT8\r
 EFIAPI\r
 PciOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -161,8 +155,8 @@ PciOr8 (
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -190,9 +184,9 @@ PciAnd8 (
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -219,9 +213,9 @@ PciAndThenOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -236,6 +230,7 @@ PciBitFieldRead8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -250,10 +245,10 @@ PciBitFieldRead8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -271,6 +266,7 @@ PciBitFieldWrite8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -285,10 +281,10 @@ PciBitFieldWrite8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -306,6 +302,7 @@ PciBitFieldOr8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -320,10 +317,10 @@ PciBitFieldOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -343,6 +340,8 @@ PciBitFieldAnd8 (
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 7, then ASSERT().\r
   If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -358,11 +357,11 @@ PciBitFieldAnd8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -384,7 +383,7 @@ PciBitFieldAndThenOr8 (
 UINT16\r
 EFIAPI\r
 PciRead16 (\r
 UINT16\r
 EFIAPI\r
 PciRead16 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -407,8 +406,8 @@ PciRead16 (
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINT16  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -435,8 +434,8 @@ PciWrite16 (
 UINT16\r
 EFIAPI\r
 PciOr16 (\r
 UINT16\r
 EFIAPI\r
 PciOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -463,8 +462,8 @@ PciOr16 (
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -493,9 +492,9 @@ PciAnd16 (
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -523,9 +522,9 @@ PciAndThenOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -541,6 +540,7 @@ PciBitFieldRead16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -555,10 +555,10 @@ PciBitFieldRead16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -577,6 +577,7 @@ PciBitFieldWrite16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -591,10 +592,10 @@ PciBitFieldWrite16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -613,6 +614,7 @@ PciBitFieldOr16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -627,10 +629,10 @@ PciBitFieldOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -651,6 +653,8 @@ PciBitFieldAnd16 (
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -666,11 +670,11 @@ PciBitFieldAnd16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -692,7 +696,7 @@ PciBitFieldAndThenOr16 (
 UINT32\r
 EFIAPI\r
 PciRead32 (\r
 UINT32\r
 EFIAPI\r
 PciRead32 (\r

-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -715,8 +719,8 @@ PciRead32 (
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINT32  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -743,8 +747,8 @@ PciWrite32 (
 UINT32\r
 EFIAPI\r
 PciOr32 (\r
 UINT32\r
 EFIAPI\r
 PciOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -771,8 +775,8 @@ PciOr32 (
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -801,9 +805,9 @@ PciAnd32 (
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -831,9 +835,9 @@ PciAndThenOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -849,6 +853,7 @@ PciBitFieldRead32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -863,10 +868,10 @@ PciBitFieldRead32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  Value\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -885,6 +890,7 @@ PciBitFieldWrite32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -899,10 +905,10 @@ PciBitFieldWrite32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -921,6 +927,7 @@ PciBitFieldOr32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -935,10 +942,10 @@ PciBitFieldOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -959,6 +966,8 @@ PciBitFieldAnd32 (
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r

+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r

 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r


@@ -974,11 +983,11 @@ PciBitFieldAnd32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r

-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -988,7 +997,7 @@ PciBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r

-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r

   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r


@@ -1007,9 +1016,9 @@ PciBitFieldAndThenOr32 (
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r

-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  OUT     VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  OUT     VOID   *Buffer\r

   );\r
 \r
 /**\r
   );\r
 \r
 /**\r


@@ -1020,7 +1029,7 @@ PciReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r

-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r

   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r


@@ -1039,9 +1048,9 @@ PciReadBuffer (
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r

-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  IN      VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  IN      VOID   *Buffer\r

   );\r
 \r
 #endif\r
   );\r
 \r
 #endif\r