UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdePkg / Include / Library / PciLib.h

diff --git a/MdePkg/Include/Library/PciLib.h b/MdePkg/Include/Library/PciLib.h
index d77c8b2c61dd7b958b1656c69977a48926616103..382a3df5b2d6562b8a7863df225ce168e10255cb 100644 (file)
--- a/MdePkg/Include/Library/PciLib.h
+++ b/MdePkg/Include/Library/PciLib.h
@@ -11,13 +11,7 @@
   explicit access methods.\r
 \r
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -37,7 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @return The encoded PCI address.\r
 \r
 **/\r
-#define PCI_LIB_ADDRESS(Bus,Device,Function,Register)   \\r
+#define PCI_LIB_ADDRESS(Bus, Device, Function, Register)   \\r
   (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
 \r
 /**\r
@@ -85,7 +79,7 @@ PciRegisterForRuntimeAccess (
 UINT8\r
 EFIAPI\r
 PciRead8 (\r
-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r
   );\r
 \r
 /**\r
@@ -107,8 +101,8 @@ PciRead8 (
 UINT8\r
 EFIAPI\r
 PciWrite8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINT8  Value\r
   );\r
 \r
 /**\r
@@ -134,8 +128,8 @@ PciWrite8 (
 UINT8\r
 EFIAPI\r
 PciOr8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  OrData\r
   );\r
 \r
 /**\r
@@ -161,8 +155,8 @@ PciOr8 (
 UINT8\r
 EFIAPI\r
 PciAnd8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData\r
   );\r
 \r
 /**\r
@@ -190,9 +184,9 @@ PciAnd8 (
 UINT8\r
 EFIAPI\r
 PciAndThenOr8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r
   );\r
 \r
 /**\r
@@ -219,9 +213,9 @@ PciAndThenOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldRead8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r
   );\r
 \r
 /**\r
@@ -251,10 +245,10 @@ PciBitFieldRead8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldWrite8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     Value\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  Value\r
   );\r
 \r
 /**\r
@@ -287,10 +281,10 @@ PciBitFieldWrite8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldOr8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  OrData\r
   );\r
 \r
 /**\r
@@ -323,10 +317,10 @@ PciBitFieldOr8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAnd8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData\r
   );\r
 \r
 /**\r
@@ -363,11 +357,11 @@ PciBitFieldAnd8 (
 UINT8\r
 EFIAPI\r
 PciBitFieldAndThenOr8 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit,\r
+  IN      UINT8  AndData,\r
+  IN      UINT8  OrData\r
   );\r
 \r
 /**\r
@@ -389,7 +383,7 @@ PciBitFieldAndThenOr8 (
 UINT16\r
 EFIAPI\r
 PciRead16 (\r
-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r
   );\r
 \r
 /**\r
@@ -412,8 +406,8 @@ PciRead16 (
 UINT16\r
 EFIAPI\r
 PciWrite16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINT16  Value\r
   );\r
 \r
 /**\r
@@ -440,8 +434,8 @@ PciWrite16 (
 UINT16\r
 EFIAPI\r
 PciOr16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  OrData\r
   );\r
 \r
 /**\r
@@ -468,8 +462,8 @@ PciOr16 (
 UINT16\r
 EFIAPI\r
 PciAnd16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData\r
   );\r
 \r
 /**\r
@@ -498,9 +492,9 @@ PciAnd16 (
 UINT16\r
 EFIAPI\r
 PciAndThenOr16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r
   );\r
 \r
 /**\r
@@ -528,9 +522,9 @@ PciAndThenOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldRead16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r
   );\r
 \r
 /**\r
@@ -561,10 +555,10 @@ PciBitFieldRead16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldWrite16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  Value\r
   );\r
 \r
 /**\r
@@ -598,10 +592,10 @@ PciBitFieldWrite16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldOr16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  OrData\r
   );\r
 \r
 /**\r
@@ -635,10 +629,10 @@ PciBitFieldOr16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAnd16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData\r
   );\r
 \r
 /**\r
@@ -676,11 +670,11 @@ PciBitFieldAnd16 (
 UINT16\r
 EFIAPI\r
 PciBitFieldAndThenOr16 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT16  AndData,\r
+  IN      UINT16  OrData\r
   );\r
 \r
 /**\r
@@ -702,7 +696,7 @@ PciBitFieldAndThenOr16 (
 UINT32\r
 EFIAPI\r
 PciRead32 (\r
-  IN      UINTN                     Address\r
+  IN      UINTN  Address\r
   );\r
 \r
 /**\r
@@ -725,8 +719,8 @@ PciRead32 (
 UINT32\r
 EFIAPI\r
 PciWrite32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINT32  Value\r
   );\r
 \r
 /**\r
@@ -753,8 +747,8 @@ PciWrite32 (
 UINT32\r
 EFIAPI\r
 PciOr32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  OrData\r
   );\r
 \r
 /**\r
@@ -781,8 +775,8 @@ PciOr32 (
 UINT32\r
 EFIAPI\r
 PciAnd32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData\r
   );\r
 \r
 /**\r
@@ -811,9 +805,9 @@ PciAnd32 (
 UINT32\r
 EFIAPI\r
 PciAndThenOr32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r
   );\r
 \r
 /**\r
@@ -841,9 +835,9 @@ PciAndThenOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldRead32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN      UINTN  Address,\r
+  IN      UINTN  StartBit,\r
+  IN      UINTN  EndBit\r
   );\r
 \r
 /**\r
@@ -874,10 +868,10 @@ PciBitFieldRead32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldWrite32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    Value\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  Value\r
   );\r
 \r
 /**\r
@@ -911,10 +905,10 @@ PciBitFieldWrite32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldOr32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  OrData\r
   );\r
 \r
 /**\r
@@ -948,10 +942,10 @@ PciBitFieldOr32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAnd32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData\r
   );\r
 \r
 /**\r
@@ -989,11 +983,11 @@ PciBitFieldAnd32 (
 UINT32\r
 EFIAPI\r
 PciBitFieldAndThenOr32 (\r
-  IN      UINTN                     Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN      UINTN   Address,\r
+  IN      UINTN   StartBit,\r
+  IN      UINTN   EndBit,\r
+  IN      UINT32  AndData,\r
+  IN      UINT32  OrData\r
   );\r
 \r
 /**\r
@@ -1003,7 +997,7 @@ PciBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be read. Size is\r
   returned. When possible 32-bit PCI configuration read cycles are used to read\r
-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
   and 16-bit PCI configuration read cycles may be used at the beginning and the\r
   end of the range.\r
 \r
@@ -1022,9 +1016,9 @@ PciBitFieldAndThenOr32 (
 UINTN\r
 EFIAPI\r
 PciReadBuffer (\r
-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  OUT     VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  OUT     VOID   *Buffer\r
   );\r
 \r
 /**\r
@@ -1035,7 +1029,7 @@ PciReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI\r
   configuration registers from a single PCI function to be written. Size is\r
   returned. When possible 32-bit PCI configuration write cycles are used to\r
-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
   and the end of the range.\r
 \r
@@ -1054,9 +1048,9 @@ PciReadBuffer (
 UINTN\r
 EFIAPI\r
 PciWriteBuffer (\r
-  IN      UINTN                     StartAddress,\r
-  IN      UINTN                     Size,\r
-  IN      VOID                      *Buffer\r
+  IN      UINTN  StartAddress,\r
+  IN      UINTN  Size,\r
+  IN      VOID   *Buffer\r
   );\r
 \r
 #endif\r