MdePkg: Clean up source files

[mirror_edk2.git] / MdePkg / Include / Library / PciSegmentLib.h

diff --git a/MdePkg/Include/Library/PciSegmentLib.h b/MdePkg/Include/Library/PciSegmentLib.h
index 6e4fecb0b1c94be8e074ba3365ea655a1e1b1edf..5eeda03988e3fd87bbd6117f05ac6453c16aa756 100644 (file)
--- a/MdePkg/Include/Library/PciSegmentLib.h
+++ b/MdePkg/Include/Library/PciSegmentLib.h
@@ -1,11 +1,11 @@
 /** @file\r
   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r
-  \r
+\r
   The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r
-  registers on PCI root bridges on any supported PCI segment.  These library services take a single \r
-  address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.  \r
+  registers on PCI root bridges on any supported PCI segment.  These library services take a single\r
+  address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.\r
   The layout of this address parameter is as follows:\r
-  \r
+\r
             PCI Register: Bits 0..11\r
             PCI Function  Bits 12..14\r
             PCI Device  Bits 15..19\r
@@ -13,17 +13,17 @@
             Reserved  Bits 28..31.  Must be 0.\r
             PCI Segment Bits 32..47\r
             Reserved  Bits 48..63.  Must be 0.\r
-            \r
+\r
   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |\r
   63             48  47    32  31           28 27         20 19    15 14      12 11         0\r
 \r
-  These functions perform PCI configuration cycles using the default PCI configuration access \r
-  method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r
-  may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r
-  access method.  Modules will typically use the PCI Segment Library for its PCI configuration \r
-  accesses when PCI Segments other than Segment #0 must be accessed.  \r
+  These functions perform PCI configuration cycles using the default PCI configuration access\r
+  method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it\r
+  may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate\r
+  access method.  Modules will typically use the PCI Segment Library for its PCI configuration\r
+  accesses when PCI Segments other than Segment #0 must be accessed.\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -71,16 +71,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   )\r
 \r
 /**\r
-  Register a PCI device so PCI configuration registers may be accessed after \r
+  Register a PCI device so PCI configuration registers may be accessed after\r
   SetVirtualAddressMap().\r
-  \r
+\r
   If any reserved bits in Address are set, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
-  \r
+\r
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function \r
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function\r
                                    after ExitBootServices().\r
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
                                    at runtime could not be mapped.\r