/** @file\r
- Functions accessing PCI configuration registers on any supported PCI segment\r
+ Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r
\r
- Copyright (c) 2006, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
+Copyright (c) 2006 - 2008, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- Module Name: PciSegmentLib.h\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
EFIAPI\r
PciSegmentRead8 (\r
IN UINT64 Address\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes an 8-bit PCI configuration register.\r
PciSegmentWrite8 (\r
IN UINT64 Address,\r
IN UINT8 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r
PciSegmentOr8 (\r
IN UINT64 Address,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
\r
PciSegmentAnd8 (\r
IN UINT64 Address,\r
IN UINT8 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
IN UINT64 Address,\r
IN UINT8 AndData,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field of a PCI configuration register.\r
IN UINT64 Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a bit field to a PCI configuration register.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT8 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads the 8-bit PCI configuration register specified by Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT8 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r
IN UINTN EndBit,\r
IN UINT8 AndData,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a 16-bit PCI configuration register.\r
EFIAPI\r
PciSegmentRead16 (\r
IN UINT64 Address\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a 16-bit PCI configuration register.\r
PciSegmentWrite16 (\r
IN UINT64 Address,\r
IN UINT16 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r
PciSegmentOr16 (\r
IN UINT64 Address,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
\r
PciSegmentAnd16 (\r
IN UINT64 Address,\r
IN UINT16 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
IN UINT64 Address,\r
IN UINT16 AndData,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field of a PCI configuration register.\r
IN UINT64 Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a bit field to a PCI configuration register.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT16 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads the 16-bit PCI configuration register specified by Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT16 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r
IN UINTN EndBit,\r
IN UINT16 AndData,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a 32-bit PCI configuration register.\r
EFIAPI\r
PciSegmentRead32 (\r
IN UINT64 Address\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a 32-bit PCI configuration register.\r
PciSegmentWrite32 (\r
IN UINT64 Address,\r
IN UINT32 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r
PciSegmentOr32 (\r
IN UINT64 Address,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
\r
PciSegmentAnd32 (\r
IN UINT64 Address,\r
IN UINT32 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
IN UINT64 Address,\r
IN UINT32 AndData,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field of a PCI configuration register.\r
IN UINT64 Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a bit field to a PCI configuration register.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT32 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads the 32-bit PCI configuration register specified by Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT32 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r
IN UINTN EndBit,\r
IN UINT32 AndData,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a range of PCI configuration registers into a caller supplied buffer.\r
IN UINT64 StartAddress,\r
IN UINTN Size,\r
OUT VOID *Buffer\r
- )\r
-;\r
+ );\r
\r
/**\r
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r
IN UINT64 StartAddress,\r
IN UINTN Size,\r
IN VOID *Buffer\r
- )\r
-;\r
+ );\r
\r
#endif\r
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