/** @file\r
Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r
- \r
+\r
The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r
- registers on PCI root bridges on any supported PCI segment. These library services take a single \r
- address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r
+ registers on PCI root bridges on any supported PCI segment. These library services take a single\r
+ address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.\r
The layout of this address parameter is as follows:\r
- \r
+\r
PCI Register: Bits 0..11\r
PCI Function Bits 12..14\r
PCI Device Bits 15..19\r
Reserved Bits 28..31. Must be 0.\r
PCI Segment Bits 32..47\r
Reserved Bits 48..63. Must be 0.\r
- \r
+\r
| Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r
63 48 47 32 31 28 27 20 19 15 14 12 11 0\r
\r
- These functions perform PCI configuration cycles using the default PCI configuration access \r
- method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r
- may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r
- access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
- accesses when PCI Segments other than Segment #0 must be accessed. \r
+ These functions perform PCI configuration cycles using the default PCI configuration access\r
+ method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it\r
+ may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate\r
+ access method. Modules will typically use the PCI Segment Library for its PCI configuration\r
+ accesses when PCI Segments other than Segment #0 must be accessed.\r
\r
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __PCI_SEGMENT_LIB__\r
#define __PCI_SEGMENT_LIB__\r
\r
-\r
/**\r
Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r
and PCI Register to an address that can be passed to the PCI Segment Library functions.\r
@return The address that is compatible with the PCI Segment Library functions.\r
\r
**/\r
-#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
- ( ((Register) & 0xfff) | \\r
- (((Function) & 0x07) << 12) | \\r
- (((Device) & 0x1f) << 15) | \\r
- (((Bus) & 0xff) << 20) | \\r
- (LShiftU64((Segment) & 0xffff, 32)) \\r
+#define PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \\r
+ ((Segment != 0) ? \\r
+ ( ((Register) & 0xfff) | \\r
+ (((Function) & 0x07) << 12) | \\r
+ (((Device) & 0x1f) << 15) | \\r
+ (((Bus) & 0xff) << 20) | \\r
+ (LShiftU64 ((Segment) & 0xffff, 32)) \\r
+ ) : \\r
+ ( ((Register) & 0xfff) | \\r
+ (((Function) & 0x07) << 12) | \\r
+ (((Device) & 0x1f) << 15) | \\r
+ (((Bus) & 0xff) << 20) \\r
+ ) \\r
)\r
\r
/**\r
- Register a PCI device so PCI configuration registers may be accessed after \r
+ Register a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
\r
Reads and returns the 8-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
- \r
+\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
@return The 8-bit PCI configuration register specified by Address.\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
followed a bitwise OR with another 8-bit value.\r
- \r
+\r
Reads the 8-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
bitwise AND followed by a bitwise OR between the read result and\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
\r
Reads and returns the 16-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- \r
+\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
@return The 16-bit PCI configuration register specified by Address.\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
\r
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
a 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
+ bitwise OR between the read result and the value specified by OrData, and\r
+ writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned. This function\r
+ must guarantee that all PCI read and write operations are serialized.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- \r
+\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param AndData The value to AND with the PCI configuration register.\r
\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
followed a bitwise OR with another 16-bit value.\r
- \r
+\r
Reads the 16-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address. \r
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r
+ the result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 16-bit port.\r
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
+ AND, writes the result back to the bit field in the 16-bit register.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
- \r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
\r
Reads and returns the 32-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
\r
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
followed a bitwise OR with another 32-bit value.\r
- \r
+\r
Reads the 32-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- \r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
AND, and writes the result back to the bit field in the 32-bit register.\r
\r
- \r
+\r
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
AND between the read result and the value specified by AndData, and writes the result\r
to the 32-bit PCI configuration register specified by Address. The value written to\r
If EndBit is less than StartBit, then ASSERT().\r
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
Size into the buffer specified by Buffer. This function only allows the PCI\r
configuration registers from a single PCI function to be read. Size is\r
returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
Size from the buffer specified by Buffer. This function only allows the PCI\r
configuration registers from a single PCI function to be written. Size is\r
returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
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