+/**\r
+ Caches a pointer PEI Services Table. \r
+ \r
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer \r
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization \r
+ Pre-EFI Initialization Core Interface Specification. \r
+ \r
+ If PeiServicesTablePointer is NULL, then ASSERT().\r
+ \r
+ @param PeiServicesTablePointer The address of PeiServices pointer.\r
+**/\r
+VOID\r
+EFIAPI\r
+SetPeiServicesTablePointer (\r
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
+ );\r
+\r
+/**\r
+ Perform CPU specific actions required to migrate the PEI Services Table \r
+ pointer from temporary RAM to permanent RAM.\r
+\r
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes \r
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes \r
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
+ For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in\r
+ a dedicated CPU register. This means that there is no memory storage \r
+ associated with storing the PEI Services Table pointer, so no additional \r
+ migration actions are required for Itanium or ARM CPUs.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MigratePeiServicesTablePointer (\r
+ VOID\r
+ );\r
+\r