MdePkg: Clean up source files

[mirror_edk2.git] / MdePkg / Include / Ppi / PciCfg2.h

diff --git a/MdePkg/Include/Ppi/PciCfg2.h b/MdePkg/Include/Ppi/PciCfg2.h
index b741cb72797a684458725561a387dd1acaab1562..5fa87ceb8046ca84625befd672f6ce606be8f766 100644 (file)
--- a/MdePkg/Include/Ppi/PciCfg2.h
+++ b/MdePkg/Include/Ppi/PciCfg2.h
@@ -1,11 +1,11 @@
 /** @file\r
   This file declares PciCfg2 PPI.\r
 \r
-  This ppi Provides platform or chipset-specific access to \r
+  This ppi Provides platform or chipset-specific access to\r
   the PCI configuration space for a specific PCI segment.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation\r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   http://opensource.org/licenses/bsd-license.php\r
@@ -14,36 +14,46 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
   @par Revision Reference:\r
-  This PPI is defined in PI\r
-  Version 1.00.\r
+  This PPI is introduced in PI Version 1.0.\r
 \r
 **/\r
 \r
 #ifndef __PEI_PCI_CFG2_H__\r
 #define __PEI_PCI_CFG2_H__\r
 \r
-#include <ProcessorBind.h>\r
-#include <Pi/PiPeiCis.h>\r
+#include <Library/BaseLib.h>\r
 \r
 #define EFI_PEI_PCI_CFG2_PPI_GUID \\r
   { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r
 \r
-\r
 typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;\r
 \r
 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r
-  (((bus) << 24) | \\r
-  ((dev) << 16) | \\r
-  ((func) << 8) | \\r
-  ((reg) < 256 ? (reg) : ((UINT64)(reg) << 32)));\r
+  (UINT64) ( \\r
+  (((UINTN) bus) << 24) | \\r
+  (((UINTN) dev) << 16) | \\r
+  (((UINTN) func) << 8) | \\r
+  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
 \r
 ///\r
 /// EFI_PEI_PCI_CFG_PPI_WIDTH\r
 ///\r
 typedef enum {\r
+  ///\r
+  ///  8-bit access\r
+  ///\r
   EfiPeiPciCfgWidthUint8  = 0,\r
+  ///\r
+  /// 16-bit access\r
+  ///\r
   EfiPeiPciCfgWidthUint16 = 1,\r
+  ///\r
+  /// 32-bit access\r
+  ///\r
   EfiPeiPciCfgWidthUint32 = 2,\r
+  ///\r
+  /// 64-bit access\r
+  ///\r
   EfiPeiPciCfgWidthUint64 = 3,\r
   EfiPeiPciCfgWidthMaximum\r
 } EFI_PEI_PCI_CFG_PPI_WIDTH;\r
@@ -52,10 +62,29 @@ typedef enum {
 /// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r
 ///\r
 typedef struct {\r
+  ///\r
+  /// 8-bit register offset within the PCI configuration space for a given device's function\r
+  /// space.\r
+  ///\r
   UINT8   Register;\r
+  ///\r
+  /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a\r
+  /// given device.\r
+  ///\r
   UINT8   Function;\r
+  ///\r
+  /// Only the 5 least-significant bits are used to encode one of 32 possible devices.\r
+  ///\r
   UINT8   Device;\r
+  ///\r
+  /// 8-bit value to encode between 0 and 255 buses.\r
+  ///\r
   UINT8   Bus;\r
+  ///\r
+  /// Register number in PCI configuration space. If this field is zero, then Register is used\r
+  /// for the register number. If this field is non-zero, then Register is ignored and this field\r
+  /// is used for the register number.\r
+  ///\r
   UINT32  ExtendedRegister;\r
 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r
 \r
@@ -95,7 +124,7 @@ EFI_STATUS
 \r
 \r
 /**\r
-  Performs a read-modify-write operation on the contents \r
+  Performs a read-modify-write operation on the contents\r
   from a given location in the PCI configuration space.\r
 \r
   @param  PeiServices     An indirect pointer to the PEI Services Table\r
@@ -131,28 +160,21 @@ EFI_STATUS
   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,\r
   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
   IN        UINT64                    Address,\r
-  IN CONST  VOID                      *SetBits,\r
-  IN CONST  VOID                      *ClearBits\r
+  IN        VOID                      *SetBits,\r
+  IN        VOID                      *ClearBits\r
 );\r
 \r
-/**\r
-  @par Ppi Description:\r
-  The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
-  controllers behind a PCI root bridge controller.\r
-\r
-  @param Read     PCI read services.  See the Read() function description.\r
-\r
-  @param Write    PCI write services.  See the Write() function description.\r
-\r
-  @param Modify   PCI read-modify-write services.  See the Modify() function description.\r
-\r
-  @param Segment  The PCI bus segment which the specified functions will access.\r
-\r
-**/\r
+///\r
+/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
+/// controllers behind a PCI root bridge controller.\r
+///\r
 struct _EFI_PEI_PCI_CFG2_PPI {\r
   EFI_PEI_PCI_CFG2_PPI_IO  Read;\r
   EFI_PEI_PCI_CFG2_PPI_IO  Write;\r
   EFI_PEI_PCI_CFG2_PPI_RW  Modify;\r
+  ///\r
+  /// The PCI bus segment which the specified functions will access.\r
+  ///\r
   UINT16                  Segment;\r
 };\r
 \r