MdePkg/ProcessorBind: add defines for page allocation granularity

[mirror_edk2.git] / MdePkg / Include / Protocol / Cpu.h

diff --git a/MdePkg/Include/Protocol/Cpu.h b/MdePkg/Include/Protocol/Cpu.h
index d8964bdf6cd8b57720ee6087dd2c7d1b00647184..1b469aa07e1a700820658bded174773398d30ca4 100644 (file)
--- a/MdePkg/Include/Protocol/Cpu.h
+++ b/MdePkg/Include/Protocol/Cpu.h
@@ -3,8 +3,8 @@
 \r
   This code abstracts the DXE core from processor implementation details.\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
-  All rights reserved. This program and the accompanying materials                          \r
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
   http://opensource.org/licenses/bsd-license.php                                            \r
@@ -24,6 +24,9 @@
 \r
 typedef struct _EFI_CPU_ARCH_PROTOCOL   EFI_CPU_ARCH_PROTOCOL;\r
 \r
+///\r
+/// The type of flush operation\r
+///\r
 typedef enum {\r
   EfiCpuFlushTypeWriteBackInvalidate,\r
   EfiCpuFlushTypeWriteBack,\r
@@ -31,6 +34,9 @@ typedef enum {
   EfiCpuMaxFlushType\r
 } EFI_CPU_FLUSH_TYPE;\r
 \r
+///\r
+/// The type of processor INIT.\r
+///\r
 typedef enum {\r
   EfiCpuInit,\r
   EfiCpuMaxInitType\r
@@ -75,7 +81,7 @@ VOID
 \r
   @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from\r
                                 the processor's data cache.\r
-  @retval EFI_UNSUPPORTEDT      The processor does not support the cache flush type specified\r
+  @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified\r
                                 by FlushType.\r
   @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed\r
                                 from the processor's data cache.\r
@@ -206,7 +212,8 @@ EFI_STATUS
                            must be between 0 and NumberOfTimers-1.\r
   @param  TimerValue       Pointer to the returned timer value.\r
   @param  TimerPeriod      A pointer to the amount of time that passes in femtoseconds for each increment\r
-                           of TimerValue.\r
+                           of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is\r
+                           returned. This parameter is optional and may be NULL.\r
 \r
   @retval EFI_SUCCESS           The processor timer value specified by TimerIndex was returned in TimerValue.\r
   @retval EFI_DEVICE_ERROR      An error occurred attempting to read one of the processor's timers.\r
@@ -237,6 +244,8 @@ EFI_STATUS
   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by\r
                                 BaseAddress and Length cannot be modified.\r
   @retval EFI_INVALID_PARAMETER Length is zero.\r
+                                Attributes specified an illegal combination of attributes that\r
+                                cannot be set together.\r
   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of\r
                                 the memory resource range.\r
   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory\r
@@ -255,13 +264,12 @@ EFI_STATUS
   );\r
 \r
 \r
-/**\r
-  @par Protocol Description:\r
-  The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
-  Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
-  vectors and exception vectors, reading internal processor timers, resetting the processor, and\r
-  determining the processor frequency.\r
-**/\r
+///\r
+/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
+/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
+/// vectors and exception vectors, reading internal processor timers, resetting the processor, and\r
+/// determining the processor frequency.\r
+///\r
 struct _EFI_CPU_ARCH_PROTOCOL {\r
   EFI_CPU_FLUSH_DATA_CACHE            FlushDataCache;\r
   EFI_CPU_ENABLE_INTERRUPT            EnableInterrupt;\r