#define EFI_CPU_ARCH_PROTOCOL_GUID \\r
{ 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
\r
-typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
+typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
\r
///\r
/// The type of flush operation\r
IN EFI_CPU_FLUSH_TYPE FlushType\r
);\r
\r
-\r
/**\r
This function enables interrupt processing by the processor.\r
\r
IN EFI_CPU_ARCH_PROTOCOL *This\r
);\r
\r
-\r
/**\r
This function disables interrupt processing by the processor.\r
\r
IN EFI_CPU_ARCH_PROTOCOL *This\r
);\r
\r
-\r
/**\r
This function retrieves the processor's current interrupt state a returns it in\r
State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
OUT BOOLEAN *State\r
);\r
\r
-\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
processor will be reset, and control will not be returned to the caller. If InitType is\r
IN EFI_CPU_INIT_TYPE InitType\r
);\r
\r
-\r
/**\r
This function registers and enables the handler specified by InterruptHandler for a processor\r
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
);\r
\r
-\r
/**\r
This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r
\r
OUT UINT64 *TimerPeriod OPTIONAL\r
);\r
\r
-\r
/**\r
This function modifies the attributes for the memory region specified by BaseAddress and\r
Length from their current attributes to the attributes specified by Attributes.\r
IN UINT64 Attributes\r
);\r
\r
-\r
///\r
/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
/// determining the processor frequency.\r
///\r
struct _EFI_CPU_ARCH_PROTOCOL {\r
- EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r
- EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r
- EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r
- EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r
- EFI_CPU_INIT Init;\r
- EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r
- EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
- EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
+ EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r
+ EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r
+ EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r
+ EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r
+ EFI_CPU_INIT Init;\r
+ EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r
+ EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
+ EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
///\r
/// The number of timers that are available in a processor. The value in this\r
/// field is a constant that must not be modified after the CPU Architectural\r
/// Protocol is installed. All consumers must treat this as a read-only field.\r
///\r
- UINT32 NumberOfTimers;\r
+ UINT32 NumberOfTimers;\r
///\r
/// The size, in bytes, of the alignment required for DMA buffer allocations.\r
/// This is typically the size of the largest data cache line in the platform.\r
/// CPU Architectural Protocol is installed. All consumers must treat this as\r
/// a read-only field.\r
///\r
- UINT32 DmaBufferAlignment;\r
+ UINT32 DmaBufferAlignment;\r
};\r
\r
-extern EFI_GUID gEfiCpuArchProtocolGuid;\r
+extern EFI_GUID gEfiCpuArchProtocolGuid;\r
\r
#endif\r