\r
This code abstracts the DXE core from processor implementation details.\r
\r
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
);\r
\r
/**\r
- This function flushes the range of addresses from Start to Start+Length \r
- from the processor's data cache. If Start is not aligned to a cache line \r
- boundary, then the bytes before Start to the preceding cache line boundary \r
- are also flushed. If Start+Length is not aligned to a cache line boundary, \r
- then the bytes past Start+Length to the end of the next cache line boundary \r
- are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
- supported. If the data cache is fully coherent with all DMA operations, then \r
- this function can just return EFI_SUCCESS. If the processor does not support \r
+ This function flushes the range of addresses from Start to Start+Length\r
+ from the processor's data cache. If Start is not aligned to a cache line\r
+ boundary, then the bytes before Start to the preceding cache line boundary\r
+ are also flushed. If Start+Length is not aligned to a cache line boundary,\r
+ then the bytes past Start+Length to the end of the next cache line boundary\r
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
+ supported. If the data cache is fully coherent with all DMA operations, then\r
+ this function can just return EFI_SUCCESS. If the processor does not support\r
flushing a range of the data cache, then the entire data cache can be flushed.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
the processor's data cache.\r
- @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r
+ @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r
by FlushType.\r
@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
from the processor's data cache.\r
\r
\r
/**\r
- This function enables interrupt processing by the processor. \r
+ This function enables interrupt processing by the processor.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
\r
\r
/**\r
- This function retrieves the processor's current interrupt state a returns it in \r
- State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
+ This function retrieves the processor's current interrupt state a returns it in\r
+ State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
are currently disabled, then FALSE is returned.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
- processor will be reset, and control will not be returned to the caller. If InitType is \r
- not supported by this processor, or the processor cannot programmatically generate an \r
- INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
+ processor will be reset, and control will not be returned to the caller. If InitType is\r
+ not supported by this processor, or the processor cannot programmatically generate an\r
+ INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r
occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
\r
/**\r
- This function registers and enables the handler specified by InterruptHandler for a processor \r
- interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
- handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+ This function registers and enables the handler specified by InterruptHandler for a processor\r
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.\r
The installed handler is called once for each processor interrupt or exception.\r
\r
@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
///\r
- /// The number of timers that are available in a processor. The value in this \r
- /// field is a constant that must not be modified after the CPU Architectural \r
+ /// The number of timers that are available in a processor. The value in this\r
+ /// field is a constant that must not be modified after the CPU Architectural\r
/// Protocol is installed. All consumers must treat this as a read-only field.\r
///\r
UINT32 NumberOfTimers;\r
///\r
- /// The size, in bytes, of the alignment required for DMA buffer allocations. \r
- /// This is typically the size of the largest data cache line in the platform. \r
- /// The value in this field is a constant that must not be modified after the \r
- /// CPU Architectural Protocol is installed. All consumers must treat this as \r
- /// a read-only field. \r
+ /// The size, in bytes, of the alignment required for DMA buffer allocations.\r
+ /// This is typically the size of the largest data cache line in the platform.\r
+ /// The value in this field is a constant that must not be modified after the\r
+ /// CPU Architectural Protocol is installed. All consumers must treat this as\r
+ /// a read-only field.\r
///\r
UINT32 DmaBufferAlignment;\r
};\r
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