/** @file\r
This files describes the CPU I/O 2 Protocol.\r
- \r
+\r
This protocol provides an I/O abstraction for a system processor. This protocol\r
is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.\r
The I/O or memory primitives can be used by the consumer of the protocol to materialize\r
bus-specific configuration cycles, such as the transitional configuration address and data\r
- ports for PCI. Only drivers that require direct access to the entire system should use this \r
- protocol. \r
- \r
+ ports for PCI. Only drivers that require direct access to the entire system should use this\r
+ protocol.\r
+\r
Note: This is a boot-services only protocol and it may not be used by runtime drivers after\r
ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime\r
protocol and can be used by runtime drivers after ExitBootServices().\r
\r
- Copyright (c) 2007 - 2010, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Revision Reference:\r
- This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2\r
Volume 5: Standards\r
\r
**/\r
} EFI_CPU_IO_PROTOCOL_WIDTH;\r
\r
/**\r
- Enables a driver to access registers in the PI CPU I/O space. \r
+ Enables a driver to access registers in the PI CPU I/O space.\r
\r
- The Io.Read() and Io.Write() functions enable a driver to access PCI controller \r
- registers in the PI CPU I/O space. \r
+ The Io.Read() and Io.Write() functions enable a driver to access PCI controller\r
+ registers in the PI CPU I/O space.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number\r
of bytes moved is Width size * Count, starting at Address.\r
@param[in, out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
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