/** @file\r
- DebugSupport protocol and supporting definitions as defined in the EFI 1.1\r
+ DebugSupport protocol and supporting definitions as defined in the UEFI2.4\r
specification.\r
\r
The DebugSupport protocol is used by source level debuggers to abstract the\r
processor and handle context save and restore operations.\r
\r
- Copyright (c) 2006, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
- Module Name: DebugSupport.h\r
+This program and the accompanying materials are licensed and made available under \r
+the terms and conditions of the BSD License that accompanies this distribution. \r
+The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php. \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
**/\r
\r
#ifndef __DEBUG_SUPPORT_H__\r
#define __DEBUG_SUPPORT_H__\r
\r
+#include <IndustryStandard/PeImage.h>\r
+\r
typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
\r
-//\r
-// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
-//\r
+///\r
+/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.\r
+///\r
#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
{ \\r
0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
}\r
\r
-//\r
-// Debug Support definitions\r
-//\r
+///\r
+/// Processor exception to be hooked.\r
+/// All exception types for IA32, X64, Itanium and EBC processors are defined.\r
+///\r
typedef INTN EFI_EXCEPTION_TYPE;\r
\r
-//\r
-// IA-32 processor exception types\r
-//\r
+///\r
+/// IA-32 processor exception types.\r
+///\r
#define EXCEPT_IA32_DIVIDE_ERROR 0\r
#define EXCEPT_IA32_DEBUG 1\r
#define EXCEPT_IA32_NMI 2\r
#define EXCEPT_IA32_MACHINE_CHECK 18\r
#define EXCEPT_IA32_SIMD 19\r
\r
-//\r
-// IA-32 processor context definition\r
-//\r
-//\r
-// FXSAVE_STATE\r
-// FP / MMX / XMM registers (see fxrstor instruction definition)\r
-//\r
+///\r
+/// FXSAVE_STATE.\r
+/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
+///\r
typedef struct {\r
UINT16 Fcw;\r
UINT16 Fsw;\r
UINT16 Ds;\r
UINT8 Reserved2[10];\r
UINT8 St0Mm0[10], Reserved3[6];\r
- UINT8 St0Mm1[10], Reserved4[6];\r
- UINT8 St0Mm2[10], Reserved5[6];\r
- UINT8 St0Mm3[10], Reserved6[6];\r
- UINT8 St0Mm4[10], Reserved7[6];\r
- UINT8 St0Mm5[10], Reserved8[6];\r
- UINT8 St0Mm6[10], Reserved9[6];\r
- UINT8 St0Mm7[10], Reserved10[6];\r
- UINT8 Reserved11[22 * 16];\r
+ UINT8 St1Mm1[10], Reserved4[6];\r
+ UINT8 St2Mm2[10], Reserved5[6];\r
+ UINT8 St3Mm3[10], Reserved6[6];\r
+ UINT8 St4Mm4[10], Reserved7[6];\r
+ UINT8 St5Mm5[10], Reserved8[6];\r
+ UINT8 St6Mm6[10], Reserved9[6];\r
+ UINT8 St7Mm7[10], Reserved10[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
+ UINT8 Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_IA32;\r
\r
+///\r
+/// IA-32 processor context definition.\r
+///\r
typedef struct {\r
UINT32 ExceptionData;\r
EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
UINT32 Dr6;\r
UINT32 Dr7;\r
UINT32 Cr0;\r
- UINT32 Cr1; \r
+ UINT32 Cr1; /* Reserved */\r
UINT32 Cr2;\r
UINT32 Cr3;\r
UINT32 Cr4;\r
UINT32 Eax;\r
} EFI_SYSTEM_CONTEXT_IA32;\r
\r
-//\r
-// IPF processor exception types\r
-//\r
+///\r
+/// x64 processor exception types.\r
+///\r
+#define EXCEPT_X64_DIVIDE_ERROR 0\r
+#define EXCEPT_X64_DEBUG 1\r
+#define EXCEPT_X64_NMI 2\r
+#define EXCEPT_X64_BREAKPOINT 3\r
+#define EXCEPT_X64_OVERFLOW 4\r
+#define EXCEPT_X64_BOUND 5\r
+#define EXCEPT_X64_INVALID_OPCODE 6\r
+#define EXCEPT_X64_DOUBLE_FAULT 8\r
+#define EXCEPT_X64_INVALID_TSS 10\r
+#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
+#define EXCEPT_X64_STACK_FAULT 12\r
+#define EXCEPT_X64_GP_FAULT 13\r
+#define EXCEPT_X64_PAGE_FAULT 14\r
+#define EXCEPT_X64_FP_ERROR 16\r
+#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
+#define EXCEPT_X64_MACHINE_CHECK 18\r
+#define EXCEPT_X64_SIMD 19\r
+\r
+///\r
+/// FXSAVE_STATE.\r
+/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
+///\r
+typedef struct {\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT64 Rip;\r
+ UINT64 DataOffset;\r
+ UINT8 Reserved1[8];\r
+ UINT8 St0Mm0[10], Reserved2[6];\r
+ UINT8 St1Mm1[10], Reserved3[6];\r
+ UINT8 St2Mm2[10], Reserved4[6];\r
+ UINT8 St3Mm3[10], Reserved5[6];\r
+ UINT8 St4Mm4[10], Reserved6[6];\r
+ UINT8 St5Mm5[10], Reserved7[6];\r
+ UINT8 St6Mm6[10], Reserved8[6];\r
+ UINT8 St7Mm7[10], Reserved9[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
+ //\r
+ // NOTE: UEFI 2.0 spec definition as follows. \r
+ //\r
+ UINT8 Reserved11[14 * 16];\r
+} EFI_FX_SAVE_STATE_X64;\r
+\r
+///\r
+/// x64 processor context definition.\r
+///\r
+typedef struct {\r
+ UINT64 ExceptionData;\r
+ EFI_FX_SAVE_STATE_X64 FxSaveState;\r
+ UINT64 Dr0;\r
+ UINT64 Dr1;\r
+ UINT64 Dr2;\r
+ UINT64 Dr3;\r
+ UINT64 Dr6;\r
+ UINT64 Dr7;\r
+ UINT64 Cr0;\r
+ UINT64 Cr1; /* Reserved */\r
+ UINT64 Cr2;\r
+ UINT64 Cr3;\r
+ UINT64 Cr4;\r
+ UINT64 Cr8;\r
+ UINT64 Rflags;\r
+ UINT64 Ldtr;\r
+ UINT64 Tr;\r
+ UINT64 Gdtr[2];\r
+ UINT64 Idtr[2];\r
+ UINT64 Rip;\r
+ UINT64 Gs;\r
+ UINT64 Fs;\r
+ UINT64 Es;\r
+ UINT64 Ds;\r
+ UINT64 Cs;\r
+ UINT64 Ss;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 Rbp;\r
+ UINT64 Rsp;\r
+ UINT64 Rbx;\r
+ UINT64 Rdx;\r
+ UINT64 Rcx;\r
+ UINT64 Rax;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+} EFI_SYSTEM_CONTEXT_X64;\r
+\r
+///\r
+/// Itanium Processor Family Exception types.\r
+///\r
#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
#define EXCEPT_IPF_DATA_TLB 2\r
#define EXCEPT_IPF_IA32_INTERCEPT 46\r
#define EXCEPT_IPF_IA32_INTERRUPT 47\r
\r
-//\r
-// IPF processor context definition\r
-//\r
+///\r
+/// IPF processor context definition.\r
+///\r
typedef struct {\r
//\r
// The first reserved field is necessary to preserve alignment for the correct\r
- // bits in UNAT and to insure F2 is 16 byte aligned..\r
+ // bits in UNAT and to insure F2 is 16 byte aligned.\r
//\r
UINT64 Reserved;\r
UINT64 R1;\r
\r
} EFI_SYSTEM_CONTEXT_IPF;\r
\r
-//\r
-// EBC processor exception types\r
-//\r
+///\r
+/// EBC processor exception types.\r
+///\r
#define EXCEPT_EBC_UNDEFINED 0\r
#define EXCEPT_EBC_DIVIDE_ERROR 1\r
#define EXCEPT_EBC_DEBUG 2\r
#define EXCEPT_EBC_BREAKPOINT 3\r
#define EXCEPT_EBC_OVERFLOW 4\r
-#define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range\r
+#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
#define EXCEPT_EBC_STACK_FAULT 6\r
#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
-#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 // malformed instruction\r
-#define EXCEPT_EBC_BAD_BREAK 9 // BREAK 0 or undefined BREAK\r
-#define EXCEPT_EBC_STEP 10 // to support debug stepping\r
-//\r
-// For coding convenience, define the maximum valid EBC exception.\r
-//\r
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
+#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
+#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
+///\r
+/// For coding convenience, define the maximum valid EBC exception.\r
+///\r
#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
\r
-//\r
-// EBC processor context definition\r
-//\r
+///\r
+/// EBC processor context definition.\r
+///\r
typedef struct {\r
UINT64 R0;\r
UINT64 R1;\r
UINT64 Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
-//\r
-// Universal EFI_SYSTEM_CONTEXT definition\r
-//\r
+\r
+\r
+///\r
+/// ARM processor exception types.\r
+///\r
+#define EXCEPT_ARM_RESET 0\r
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
+#define EXCEPT_ARM_PREFETCH_ABORT 3\r
+#define EXCEPT_ARM_DATA_ABORT 4\r
+#define EXCEPT_ARM_RESERVED 5\r
+#define EXCEPT_ARM_IRQ 6\r
+#define EXCEPT_ARM_FIQ 7\r
+\r
+///\r
+/// For coding convenience, define the maximum valid ARM exception.\r
+///\r
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
+\r
+///\r
+/// ARM processor context definition.\r
+///\r
+typedef struct {\r
+ UINT32 R0;\r
+ UINT32 R1;\r
+ UINT32 R2;\r
+ UINT32 R3;\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 SP;\r
+ UINT32 LR;\r
+ UINT32 PC;\r
+ UINT32 CPSR;\r
+ UINT32 DFSR;\r
+ UINT32 DFAR;\r
+ UINT32 IFSR;\r
+ UINT32 IFAR;\r
+} EFI_SYSTEM_CONTEXT_ARM;\r
+\r
+\r
+///\r
+/// AARCH64 processor exception types.\r
+///\r
+#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
+#define EXCEPT_AARCH64_IRQ 1\r
+#define EXCEPT_AARCH64_FIQ 2\r
+#define EXCEPT_AARCH64_SERROR 3\r
+\r
+///\r
+/// For coding convenience, define the maximum valid ARM exception.\r
+///\r
+#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
+\r
+typedef struct {\r
+ // General Purpose Registers\r
+ UINT64 X0;\r
+ UINT64 X1;\r
+ UINT64 X2;\r
+ UINT64 X3;\r
+ UINT64 X4;\r
+ UINT64 X5;\r
+ UINT64 X6;\r
+ UINT64 X7;\r
+ UINT64 X8;\r
+ UINT64 X9;\r
+ UINT64 X10;\r
+ UINT64 X11;\r
+ UINT64 X12;\r
+ UINT64 X13;\r
+ UINT64 X14;\r
+ UINT64 X15;\r
+ UINT64 X16;\r
+ UINT64 X17;\r
+ UINT64 X18;\r
+ UINT64 X19;\r
+ UINT64 X20;\r
+ UINT64 X21;\r
+ UINT64 X22;\r
+ UINT64 X23;\r
+ UINT64 X24;\r
+ UINT64 X25;\r
+ UINT64 X26;\r
+ UINT64 X27;\r
+ UINT64 X28;\r
+ UINT64 FP; // x29 - Frame pointer\r
+ UINT64 LR; // x30 - Link Register\r
+ UINT64 SP; // x31 - Stack pointer\r
+\r
+ // FP/SIMD Registers\r
+ UINT64 V0[2];\r
+ UINT64 V1[2];\r
+ UINT64 V2[2];\r
+ UINT64 V3[2];\r
+ UINT64 V4[2];\r
+ UINT64 V5[2];\r
+ UINT64 V6[2];\r
+ UINT64 V7[2];\r
+ UINT64 V8[2];\r
+ UINT64 V9[2];\r
+ UINT64 V10[2];\r
+ UINT64 V11[2];\r
+ UINT64 V12[2];\r
+ UINT64 V13[2];\r
+ UINT64 V14[2];\r
+ UINT64 V15[2];\r
+ UINT64 V16[2];\r
+ UINT64 V17[2];\r
+ UINT64 V18[2];\r
+ UINT64 V19[2];\r
+ UINT64 V20[2];\r
+ UINT64 V21[2];\r
+ UINT64 V22[2];\r
+ UINT64 V23[2];\r
+ UINT64 V24[2];\r
+ UINT64 V25[2];\r
+ UINT64 V26[2];\r
+ UINT64 V27[2];\r
+ UINT64 V28[2];\r
+ UINT64 V29[2];\r
+ UINT64 V30[2];\r
+ UINT64 V31[2];\r
+\r
+ UINT64 ELR; // Exception Link Register\r
+ UINT64 SPSR; // Saved Processor Status Register\r
+ UINT64 FPSR; // Floating Point Status Register\r
+ UINT64 ESR; // Exception syndrome register\r
+ UINT64 FAR; // Fault Address Register\r
+} EFI_SYSTEM_CONTEXT_AARCH64;\r
+\r
+\r
+///\r
+/// Universal EFI_SYSTEM_CONTEXT definition.\r
+///\r
typedef union {\r
EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
+ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
/** \r
Registers and enables an exception callback function for the specified exception.\r
\r
- @param ExceptionType Exception types in EBC, IA-32, X64, or IPF\r
+ @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.\r
@param SystemContext Exception content.\r
\r
**/\r
typedef\r
VOID\r
-(*EFI_EXCEPTION_CALLBACK) (\r
+(EFIAPI *EFI_EXCEPTION_CALLBACK)(\r
IN EFI_EXCEPTION_TYPE ExceptionType,\r
IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
/** \r
- Registers and enables the on-target debug agent¡¯s periodic entry point.\r
+ Registers and enables the on-target debug agent's periodic entry point.\r
\r
@param SystemContext Exception content.\r
\r
**/\r
typedef\r
VOID\r
-(*EFI_PERIODIC_CALLBACK) (\r
+(EFIAPI *EFI_PERIODIC_CALLBACK)(\r
IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
-//\r
-// Machine type definition\r
-//\r
+///\r
+/// Machine type definition\r
+///\r
typedef enum {\r
- IsaIa32 = IMAGE_FILE_MACHINE_I386, // 0x014C\r
- IsaX64 = IMAGE_FILE_MACHINE_X64, // 0x8664\r
- IsaIpf = IMAGE_FILE_MACHINE_IA64, // 0x0200\r
- IsaEbc = IMAGE_FILE_MACHINE_EBC // 0x0EBC\r
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
+ IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
+ IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX) (\r
+(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r
IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
OUT UINTN *MaxProcessorIndex\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK) (\r
+(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r
IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
IN UINTN ProcessorIndex,\r
IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
\r
@param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
@param ProcessorIndex Specifies which processor the callback function applies to.\r
- @param PeriodicCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
+ @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
when the processor exception specified by ExceptionType occurs. \r
@param ExceptionType Specifies which processor exception to hook. \r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK) (\r
+(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r
IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
IN UINTN ProcessorIndex,\r
IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
causes a fresh memory fetch to retrieve code to be executed. \r
\r
@param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
- @param ProcessorIndex Specifies which processor¡¯s instruction cache is to be invalidated.\r
+ @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
@param Start Specifies the physical base of the memory range to be invalidated. \r
- @param Length Specifies the minimum number of bytes in the processor¡¯s instruction\r
+ @param Length Specifies the minimum number of bytes in the processor's instruction\r
cache to invalidate. \r
\r
@retval EFI_SUCCESS The function completed successfully. \r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE) (\r
+(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r
IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
IN UINTN ProcessorIndex,\r
IN VOID *Start,\r
IN UINT64 Length\r
);\r
\r
-//\r
-// DebugSupport protocol definition\r
-//\r
+///\r
+/// This protocol provides the services to allow the debug agent to register \r
+/// callback functions that are called either periodically or when specific \r
+/// processor exceptions occur.\r
+///\r
struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
+ ///\r
+ /// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r
+ ///\r
EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
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