The DebugSupport protocol is used by source level debuggers to abstract the\r
processor and handle context save and restore operations.\r
\r
- Copyright (c) 2006 - 2009, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials are licensed and made available under \r
+the terms and conditions of the BSD License that accompanies this distribution. \r
+The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php. \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
**/\r
\r
#ifndef __DEBUG_SUPPORT_H__\r
#define __DEBUG_SUPPORT_H__\r
\r
-#include <ProcessorBind.h>\r
#include <IndustryStandard/PeImage.h>\r
\r
typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
\r
///\r
-/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
+/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.\r
///\r
#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
{ \\r
typedef INTN EFI_EXCEPTION_TYPE;\r
\r
///\r
-/// IA-32 processor exception types\r
+/// IA-32 processor exception types.\r
///\r
#define EXCEPT_IA32_DIVIDE_ERROR 0\r
#define EXCEPT_IA32_DEBUG 1\r
#define EXCEPT_IA32_SIMD 19\r
\r
///\r
-/// FXSAVE_STATE\r
-/// FP / MMX / XMM registers (see fxrstor instruction definition)\r
+/// FXSAVE_STATE.\r
+/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
///\r
typedef struct {\r
UINT16 Fcw;\r
} EFI_FX_SAVE_STATE_IA32;\r
\r
///\r
-/// IA-32 processor context definition\r
+/// IA-32 processor context definition.\r
///\r
typedef struct {\r
UINT32 ExceptionData;\r
} EFI_SYSTEM_CONTEXT_IA32;\r
\r
///\r
-/// x64 processor exception types\r
+/// x64 processor exception types.\r
///\r
#define EXCEPT_X64_DIVIDE_ERROR 0\r
#define EXCEPT_X64_DEBUG 1\r
#define EXCEPT_X64_SIMD 19\r
\r
///\r
-/// FXSAVE_STATE\r
-/// FP / MMX / XMM registers (see fxrstor instruction definition)\r
+/// FXSAVE_STATE.\r
+/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
///\r
typedef struct {\r
UINT16 Fcw;\r
} EFI_FX_SAVE_STATE_X64;\r
\r
///\r
-/// x64 processor context definition\r
+/// x64 processor context definition.\r
///\r
typedef struct {\r
UINT64 ExceptionData;\r
} EFI_SYSTEM_CONTEXT_X64;\r
\r
///\r
-/// Itanium Processor Family Exception types\r
+/// Itanium Processor Family Exception types.\r
///\r
#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
#define EXCEPT_IPF_IA32_INTERRUPT 47\r
\r
///\r
-/// IPF processor context definition\r
+/// IPF processor context definition.\r
///\r
typedef struct {\r
//\r
// The first reserved field is necessary to preserve alignment for the correct\r
- // bits in UNAT and to insure F2 is 16 byte aligned..\r
+ // bits in UNAT and to insure F2 is 16 byte aligned.\r
//\r
UINT64 Reserved;\r
UINT64 R1;\r
} EFI_SYSTEM_CONTEXT_IPF;\r
\r
///\r
-/// EBC processor exception types\r
+/// EBC processor exception types.\r
///\r
#define EXCEPT_EBC_UNDEFINED 0\r
#define EXCEPT_EBC_DIVIDE_ERROR 1\r
#define EXCEPT_EBC_DEBUG 2\r
#define EXCEPT_EBC_BREAKPOINT 3\r
#define EXCEPT_EBC_OVERFLOW 4\r
-#define EXCEPT_EBC_INVALID_OPCODE 5 ///< opcode out of range\r
+#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
#define EXCEPT_EBC_STACK_FAULT 6\r
#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
-#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< malformed instruction\r
-#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK\r
-#define EXCEPT_EBC_STEP 10 ///< to support debug stepping\r
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
+#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
+#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
///\r
/// For coding convenience, define the maximum valid EBC exception.\r
///\r
#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
\r
///\r
-/// EBC processor context definition\r
+/// EBC processor context definition.\r
///\r
typedef struct {\r
UINT64 R0;\r
UINT64 Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
+\r
+\r
+///\r
+/// ARM processor exception types.\r
+///\r
+#define EXCEPT_ARM_RESET 0\r
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
+#define EXCEPT_ARM_PREFETCH_ABORT 3\r
+#define EXCEPT_ARM_DATA_ABORT 4\r
+#define EXCEPT_ARM_RESERVED 5\r
+#define EXCEPT_ARM_IRQ 6\r
+#define EXCEPT_ARM_FIQ 7\r
+\r
+///\r
+/// For coding convenience, define the maximum valid ARM exception.\r
+///\r
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
+\r
+///\r
+/// ARM processor context definition.\r
///\r
-/// Universal EFI_SYSTEM_CONTEXT definition\r
+typedef struct {\r
+ UINT32 R0;\r
+ UINT32 R1;\r
+ UINT32 R2;\r
+ UINT32 R3;\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 SP;\r
+ UINT32 LR;\r
+ UINT32 PC;\r
+ UINT32 CPSR;\r
+ UINT32 DFSR;\r
+ UINT32 DFAR;\r
+ UINT32 IFSR;\r
+ UINT32 IFAR;\r
+} EFI_SYSTEM_CONTEXT_ARM;\r
+\r
+///\r
+/// Universal EFI_SYSTEM_CONTEXT definition.\r
///\r
typedef union {\r
EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
/** \r
Registers and enables an exception callback function for the specified exception.\r
\r
- @param ExceptionType Exception types in EBC, IA-32, x64, or IPF\r
+ @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.\r
@param SystemContext Exception content.\r
\r
**/\r
/// Machine type definition\r
///\r
typedef enum {\r
- IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
- IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
- IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
- IsaEbc = IMAGE_FILE_MACHINE_EBC ///< 0x0EBC\r
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
+ IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED ///< 0x01c2\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
\r
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