/** @file\r
- Device IO protocol as defined in the EFI 1.0 specification.\r
+ Device IO protocol as defined in the EFI 1.10 specification.\r
\r
Device IO is used to abstract hardware access to devices. It includes\r
memory mapped IO, IO, PCI Config space, and DMA.\r
\r
- Copyright (c) 2006, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
- Module Name: DeviceIo.h\r
-\r
**/\r
\r
#ifndef __DEVICE_IO_H__\r
\r
typedef struct _EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL;\r
\r
+///\r
+/// Protocol GUID name defined in EFI1.1.\r
+/// \r
+#define DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL_GUID\r
+\r
+///\r
+/// Protocol defined in EFI1.1.\r
+/// \r
+typedef EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_INTERFACE;\r
+\r
+///\r
+/// Device IO Access Width \r
+///\r
typedef enum {\r
- IO_UINT8,\r
- IO_UINT16,\r
- IO_UINT32,\r
- IO_UINT64,\r
- MMIO_COPY_UINT8,\r
- MMIO_COPY_UINT16,\r
- MMIO_COPY_UINT32,\r
- MMIO_COPY_UINT64\r
+ IO_UINT8 = 0,\r
+ IO_UINT16 = 1,\r
+ IO_UINT32 = 2,\r
+ IO_UINT64 = 3,\r
+ //\r
+ // Below enumerations are added in "Extensible Firmware Interface Specification, \r
+ // Version 1.10, Specification Update, Version 001".\r
+ //\r
+ MMIO_COPY_UINT8 = 4,\r
+ MMIO_COPY_UINT16 = 5,\r
+ MMIO_COPY_UINT32 = 6,\r
+ MMIO_COPY_UINT64 = 7\r
} EFI_IO_WIDTH;\r
\r
/** \r
@param Address The base address of the I/O operations. \r
@param Count The number of I/O operations to perform.\r
@param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from. \r
+ operations, the source buffer to write data from. If\r
+ Width is MMIO_COPY_UINT8, MMIO_COPY_UINT16,\r
+ MMIO_COPY_UINT32, or MMIO_COPY_UINT64, then\r
+ Buffer is interpreted as a base address of an I/O operation such as Address. \r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DEVICE_IO) (\r
+(EFIAPI *EFI_DEVICE_IO)(\r
IN EFI_DEVICE_IO_PROTOCOL *This,\r
IN EFI_IO_WIDTH Width,\r
IN UINT64 Address,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_DEVICE_PATH) (\r
+(EFIAPI *EFI_PCI_DEVICE_PATH)(\r
IN EFI_DEVICE_IO_PROTOCOL *This,\r
IN UINT64 PciAddress,\r
IN OUT EFI_DEVICE_PATH_PROTOCOL **PciDevicePath\r
);\r
\r
typedef enum {\r
+ ///\r
+ /// A read operation from system memory by a bus master.\r
+ ///\r
EfiBusMasterRead,\r
+\r
+ ///\r
+ /// A write operation to system memory by a bus master.\r
+ ///\r
EfiBusMasterWrite,\r
+ \r
+ ///\r
+ /// Provides both read and write access to system memory\r
+ /// by both the processor and a bus master. The buffer is\r
+ /// coherent from both the processor's and the bus master's\r
+ /// point of view.\r
+ ///\r
EfiBusMasterCommonBuffer\r
} EFI_IO_OPERATION_TYPE;\r
\r
@param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.\r
@param Operation Indicates if the bus master is going to read or write to system memory.\r
@param HostAddress The system memory address to map to the device.\r
- @param NumberOfBytes On input the number of bytes to map.\r
+ @param NumberOfBytes On input, the number of bytes to map.\r
+ On output, the number of bytes that were mapped.\r
@param DeviceAddress The resulting map address for the bus master device to use to access the\r
hosts HostAddress.\r
@param Mapping A resulting value to pass to Unmap().\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IO_MAP) (\r
+(EFIAPI *EFI_IO_MAP)(\r
IN EFI_DEVICE_IO_PROTOCOL *This,\r
IN EFI_IO_OPERATION_TYPE Operation,\r
IN EFI_PHYSICAL_ADDRESS *HostAddress,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IO_UNMAP) (\r
+(EFIAPI *EFI_IO_UNMAP)(\r
IN EFI_DEVICE_IO_PROTOCOL *This,\r
IN VOID *Mapping\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IO_ALLOCATE_BUFFER) (\r
+(EFIAPI *EFI_IO_ALLOCATE_BUFFER)(\r
IN EFI_DEVICE_IO_PROTOCOL *This,\r
IN EFI_ALLOCATE_TYPE Type,\r
IN EFI_MEMORY_TYPE MemoryType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IO_FLUSH) (\r
+(EFIAPI *EFI_IO_FLUSH)(\r
IN EFI_DEVICE_IO_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IO_FREE_BUFFER) (\r
+(EFIAPI *EFI_IO_FREE_BUFFER)(\r
IN EFI_DEVICE_IO_PROTOCOL *This,\r
IN UINTN Pages,\r
IN EFI_PHYSICAL_ADDRESS HostAddress\r
);\r
\r
+///\r
+/// This protocol provides the basic Memory, I/O, and PCI interfaces that \r
+/// are used to abstract accesses to devices.\r
+///\r
struct _EFI_DEVICE_IO_PROTOCOL {\r
+ ///\r
+ /// Allows reads and writes to memory mapped I/O space.\r
+ ///\r
EFI_IO_ACCESS Mem;\r
+ ///\r
+ /// Allows reads and writes to I/O space.\r
+ ///\r
EFI_IO_ACCESS Io;\r
+ ///\r
+ /// Allows reads and writes to PCI configuration space.\r
+ ///\r
EFI_IO_ACCESS Pci;\r
EFI_IO_MAP Map;\r
EFI_PCI_DEVICE_PATH PciDevicePath;\r
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