and DMA interfaces that a driver uses to access its PCI controller.\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
}\r
\r
-typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
+typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
/// *******************************************************\r
///\r
typedef enum {\r
- EfiPciIoWidthUint8 = 0,\r
+ EfiPciIoWidthUint8 = 0,\r
EfiPciIoWidthUint16,\r
EfiPciIoWidthUint32,\r
EfiPciIoWidthUint64,\r
//\r
// Complete PCI address generater\r
//\r
-#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
-#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
-#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
-#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
-#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
-#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
-\r
-#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
-#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
+#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
+#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
+#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
+#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
+#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
+#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
+\r
+#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
+#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
///\r
/// *******************************************************\r
///\r
/// Read PCI controller registers in the PCI memory or I/O space.\r
///\r
- EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
+ EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
///\r
/// Write PCI controller registers in the PCI memory or I/O space.\r
///\r
- EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
+ EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
/**\r
///\r
/// Read PCI controller registers in PCI configuration space.\r
///\r
- EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
+ EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
///\r
/// Write PCI controller registers in PCI configuration space.\r
///\r
- EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
+ EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
/**\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN UINT8 BarIndex,\r
- OUT UINT64 *Supports, OPTIONAL\r
+ OUT UINT64 *Supports OPTIONAL,\r
OUT VOID **Resources OPTIONAL\r
);\r
\r
/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.\r
///\r
struct _EFI_PCI_IO_PROTOCOL {\r
- EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
- EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
- EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
- EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
- EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
- EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
- EFI_PCI_IO_PROTOCOL_MAP Map;\r
- EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
- EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
- EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
- EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
- EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
- EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
- EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
- EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
+ EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
+ EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
+ EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
+ EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
+ EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
+ EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
+ EFI_PCI_IO_PROTOCOL_MAP Map;\r
+ EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
+ EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
+ EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
+ EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
+ EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
+ EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
+ EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
+ EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
\r
///\r
/// The size, in bytes, of the ROM image.\r
///\r
- UINT64 RomSize;\r
+ UINT64 RomSize;\r
\r
///\r
/// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible\r
/// The Attributes() function can be used to determine from which of these two sources\r
/// the RomImage buffer was initialized.\r
///\r
- VOID *RomImage;\r
+ VOID *RomImage;\r
};\r
\r
-extern EFI_GUID gEfiPciIoProtocolGuid;\r
+extern EFI_GUID gEfiPciIoProtocolGuid;\r
\r
#endif\r
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