EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, \r
and DMA interfaces that a driver uses to access its PCI controller.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
\r
///\r
-/// Prototypes for the PCI I/O Protocol\r
+/// *******************************************************\r
+/// EFI_PCI_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
///\r
typedef enum {\r
EfiPciIoWidthUint8 = 0,\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so write are combined\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
\r
#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
/// *******************************************************\r
///\r
typedef enum {\r
+ ///\r
+ /// A read operation from system memory by a bus master.\r
+ ///\r
EfiPciIoOperationBusMasterRead,\r
+ ///\r
+ /// A write operation from system memory by a bus master.\r
+ ///\r
EfiPciIoOperationBusMasterWrite,\r
+ ///\r
+ /// Provides both read and write access to system memory by both the processor and a\r
+ /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r
+ ///\r
EfiPciIoOperationBusMasterCommonBuffer,\r
EfiPciIoOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_OPERATION;\r
/// *******************************************************\r
///\r
typedef enum {\r
+ ///\r
+ /// Retrieve the PCI controller's current attributes, and return them in Result.\r
+ ///\r
EfiPciIoAttributeOperationGet,\r
+ ///\r
+ /// Set the PCI controller's current attributes to Attributes.\r
+ ///\r
EfiPciIoAttributeOperationSet,\r
+ ///\r
+ /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
+ ///\r
EfiPciIoAttributeOperationEnable,\r
+ ///\r
+ /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
+ ///\r
EfiPciIoAttributeOperationDisable,\r
+ ///\r
+ /// Retrieve the PCI controller's supported attributes, and return them in Result.\r
+ ///\r
EfiPciIoAttributeOperationSupported,\r
EfiPciIoAttributeOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
\r
/** \r
- Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration. \r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
);\r
\r
typedef struct {\r
+ ///\r
+ /// Read PCI controller registers in the PCI memory or I/O space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
+ ///\r
+ /// Write PCI controller registers in the PCI memory or I/O space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
);\r
\r
typedef struct {\r
+ ///\r
+ /// Read PCI controller registers in PCI configuration space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
+ ///\r
+ /// Write PCI controller registers in PCI configuration space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
);\r
\r
/** \r
- Provides the PCI controller-Cspecific addresses needed to access system memory.\r
+ Provides the PCI controller-specific addresses needed to access system memory.\r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation Indicates if the bus master is going to read or write to system memory.\r
IN OUT UINT64 *Length\r
);\r
\r
-/** \r
- @par Protocol Description:\r
- The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, \r
- and DMA interfaces that are used to abstract accesses to PCI controllers. \r
- There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. \r
- A device driver that wishes to manage a PCI controller in a system will have to \r
- retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. \r
-**/\r
+///\r
+/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, \r
+/// and DMA interfaces used to abstract accesses to PCI controllers. \r
+/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. \r
+/// A device driver that wishes to manage a PCI controller in a system will have to \r
+/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. \r
+///\r
struct _EFI_PCI_IO_PROTOCOL {\r
EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
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