/** @file\r
- EFI PCI I/O Protocol\r
+ EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, \r
+ and DMA interfaces that a driver uses to access its PCI controller.\r
\r
- Copyright (c) 2006, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
- Module Name: PciIo.h\r
-\r
**/\r
\r
#ifndef __PCI_IO_H__\r
#define __PCI_IO_H__\r
\r
-//\r
-// Global ID for the PCI I/O Protocol\r
-//\r
+///\r
+/// Global ID for the PCI I/O Protocol\r
+///\r
#define EFI_PCI_IO_PROTOCOL_GUID \\r
{ \\r
0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
\r
typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
\r
-//\r
-// Prototypes for the PCI I/O Protocol\r
-//\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
+///\r
typedef enum {\r
EfiPciIoWidthUint8 = 0,\r
EfiPciIoWidthUint16,\r
//\r
// Complete PCI address generater\r
//\r
-#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff // Special BAR that passes a memory or I/O cycle through unchanged\r
-#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f // All the following I/O and Memory cycles\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 // I/O cycles 0x0000-0x00FF (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 // I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 // MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 // I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 // I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 // Map a memory range so write are combined\r
-#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 // Enable the I/O decode bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 // Enable the Memory decode bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 // Enable the DMA bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 // Map a memory range so all r/w accesses are cached\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range\r
-#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 // Clear for an add-in PCI Device\r
-#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 // Clear for a physical PCI Option ROM accessed through ROM BAR\r
-#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 // Clear for PCI controllers that can not genrate a DAC\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 // I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 // I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 // I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
+#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
+#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
+#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
+#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
+#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
+#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
\r
#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
-//\r
-// *******************************************************\r
-// EFI_PCI_IO_PROTOCOL_OPERATION\r
-// *******************************************************\r
-//\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_IO_PROTOCOL_OPERATION\r
+/// *******************************************************\r
+///\r
typedef enum {\r
+ ///\r
+ /// A read operation from system memory by a bus master.\r
+ ///\r
EfiPciIoOperationBusMasterRead,\r
+ ///\r
+ /// A write operation from system memory by a bus master.\r
+ ///\r
EfiPciIoOperationBusMasterWrite,\r
+ ///\r
+ /// Provides both read and write access to system memory by both the processor and a\r
+ /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r
+ ///\r
EfiPciIoOperationBusMasterCommonBuffer,\r
EfiPciIoOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_OPERATION;\r
\r
-//\r
-// *******************************************************\r
-// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
-// *******************************************************\r
-//\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
+/// *******************************************************\r
+///\r
typedef enum {\r
+ ///\r
+ /// Retrieve the PCI controller's current attributes, and return them in Result.\r
+ ///\r
EfiPciIoAttributeOperationGet,\r
+ ///\r
+ /// Set the PCI controller's current attributes to Attributes.\r
+ ///\r
EfiPciIoAttributeOperationSet,\r
+ ///\r
+ /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
+ ///\r
EfiPciIoAttributeOperationEnable,\r
+ ///\r
+ /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
+ ///\r
EfiPciIoAttributeOperationDisable,\r
+ ///\r
+ /// Retrieve the PCI controller's supported attributes, and return them in Result.\r
+ ///\r
EfiPciIoAttributeOperationSupported,\r
EfiPciIoAttributeOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
\r
/** \r
- Reads from the memory space of a PCI controller. Returns when either the polling exit criteria is\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
satisfied or after a defined duration. \r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
IN UINT8 BarIndex,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
IN UINT8 BarIndex,\r
);\r
\r
typedef struct {\r
+ ///\r
+ /// Read PCI controller registers in the PCI memory or I/O space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
+ ///\r
+ /// Write PCI controller registers in the PCI memory or I/O space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
IN UINT32 Offset,\r
);\r
\r
typedef struct {\r
+ ///\r
+ /// Read PCI controller registers in PCI configuration space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
+ ///\r
+ /// Write PCI controller registers in PCI configuration space.\r
+ ///\r
EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
IN UINT8 DestBarIndex,\r
);\r
\r
/** \r
- Provides the PCI controller¨Cspecific addresses needed to access system memory.\r
+ Provides the PCI controller-specific addresses needed to access system memory.\r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Operation Indicates if the bus master is going to read or write to system memory.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
IN VOID *HostAddress,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN VOID *Mapping\r
);\r
\r
/** \r
Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
- mapping. \r
+ or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Type This parameter is not used and must be ignored.\r
\r
@retval EFI_SUCCESS The requested memory pages were allocated.\r
@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
- MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_ALLOCATE_TYPE Type,\r
IN EFI_MEMORY_TYPE MemoryType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN UINTN Pages,\r
IN VOID *HostAddress\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)(\r
IN EFI_PCI_IO_PROTOCOL *This\r
);\r
\r
/** \r
- Retrieves this PCI controller¡¯s current PCI bus number, device number, and function number.\r
+ Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
- @param SegmentNumber The PCI controller¡¯s current PCI segment number.\r
- @param BusNumber The PCI controller¡¯s current PCI bus number.\r
- @param DeviceNumber The PCI controller¡¯s current PCI device number.\r
- @param FunctionNumber The PCI controller¡¯s current PCI function number.\r
+ @param SegmentNumber The PCI controller's current PCI segment number.\r
+ @param BusNumber The PCI controller's current PCI bus number.\r
+ @param DeviceNumber The PCI controller's current PCI device number.\r
+ @param FunctionNumber The PCI controller's current PCI function number.\r
\r
@retval EFI_SUCCESS The PCI controller location was returned. \r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
OUT UINTN *SegmentNumber,\r
OUT UINTN *BusNumber,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
IN UINT64 Attributes,\r
OUT UINT64 *Result OPTIONAL\r
);\r
\r
-/** \r
+/**\r
Gets the attributes that this PCI controller supports setting on a BAR using\r
SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
- \r
- @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
base address for resource range. The legal range for this field is 0..5.\r
@param Supports A pointer to the mask of attributes that this PCI controller supports\r
- setting for this BAR with SetBarAttributes(). \r
- @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
- configuration of this BAR of the PCI controller. \r
+ setting for this BAR with SetBarAttributes().\r
+ @param Resources A pointer to the resource descriptors that describe the current\r
+ configuration of this BAR of the PCI controller.\r
\r
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r
- controller supports are returned in Supports. If Resources \r
- is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
- controller is currently using are returned in Resources. \r
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
+ controller supports are returned in Supports. If Resources\r
+ is not NULL, then the resource descriptors that the PCI\r
+ controller is currently using are returned in Resources.\r
@retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
@retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
- Resources. \r
- \r
+ Resources.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN UINT8 BarIndex,\r
OUT UINT64 *Supports, OPTIONAL\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)(\r
IN EFI_PCI_IO_PROTOCOL *This,\r
IN UINT64 Attributes,\r
IN UINT8 BarIndex,\r
IN OUT UINT64 *Length\r
);\r
\r
-//\r
-// Interface structure for the PCI I/O Protocol\r
-//\r
+///\r
+/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, \r
+/// and DMA interfaces used to abstract accesses to PCI controllers. \r
+/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. \r
+/// A device driver that wishes to manage a PCI controller in a system will have to \r
+/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. \r
+///\r
struct _EFI_PCI_IO_PROTOCOL {\r
EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
+ \r
+ ///\r
+ /// The size, in bytes, of the ROM image.\r
+ ///\r
UINT64 RomSize;\r
+\r
+ ///\r
+ /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible \r
+ /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. \r
+ /// The contents of this buffer are either from the PCI option ROM that can be accessed \r
+ /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. \r
+ /// The Attributes() function can be used to determine from which of these two sources \r
+ /// the RomImage buffer was initialized.\r
+ /// \r
VOID *RomImage;\r
};\r
\r
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