EfiPciIoOperationBusMasterWrite,\r
///\r
/// Provides both read and write access to system memory by both the processor and a\r
- /// bus master. The buffer is coherent from both the processor¡¯s and the bus master's point of view.\r
+ /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r
///\r
EfiPciIoOperationBusMasterCommonBuffer,\r
EfiPciIoOperationMaximum\r
///\r
typedef enum {\r
///\r
- /// Retrieve the PCI controller¡¯s current attributes, and return them in Result.\r
+ /// Retrieve the PCI controller's current attributes, and return them in Result.\r
///\r
EfiPciIoAttributeOperationGet,\r
///\r
- /// Set the PCI controller¡¯s current attributes to Attributes.\r
+ /// Set the PCI controller's current attributes to Attributes.\r
///\r
EfiPciIoAttributeOperationSet,\r
///\r