\r
PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
- defferent types of bus mastering DMA\r
+ defferent types of bus mastering DMA.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
#define __PCI_ROOT_BRIDGE_IO_H__\r
\r
+#include <Library/BaseLib.h>\r
+\r
#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
{ \\r
0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
\r
typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
+///\r
typedef enum {\r
EfiPciWidthUint8,\r
EfiPciWidthUint16,\r
EfiPciWidthMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
+/// *******************************************************\r
+///\r
typedef enum {\r
+ ///\r
+ /// A read operation from system memory by a bus master that is not capable of producing\r
+ /// PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterRead,\r
+ ///\r
+ /// A write operation from system memory by a bus master that is not capable of producing\r
+ /// PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterWrite,\r
+ ///\r
+ /// Provides both read and write access to system memory by both the processor and a bus\r
+ /// master that is not capable of producing PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterCommonBuffer,\r
+ ///\r
+ /// A read operation from system memory by a bus master that is capable of producing PCI\r
+ /// dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterRead64,\r
+ ///\r
+ /// A write operation to system memory by a bus master that is capable of producing PCI\r
+ /// dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterWrite64,\r
+ ///\r
+ /// Provides both read and write access to system memory by both the processor and a bus\r
+ /// master that is capable of producing PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterCommonBuffer64,\r
EfiPciOperationMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800\r
#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000\r
#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000\r
+#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000\r
+#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000\r
+#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000\r
\r
#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
\r
#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
\r
#define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
- ((UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)))\r
+ (UINT64) ( \\r
+ (((UINTN) bus) << 24) | \\r
+ (((UINTN) dev) << 16) | \\r
+ (((UINTN) func) << 8) | \\r
+ (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
\r
typedef struct {\r
UINT8 Register;\r
);\r
\r
typedef struct {\r
+ ///\r
+ /// Read PCI controller registers in the PCI root bridge memory space.\r
+ ///\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;\r
+ ///\r
+ /// Write PCI controller registers in the PCI root bridge memory space.\r
+ ///\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
\r
);\r
\r
/** \r
- Provides the PCI controller-Cspecific addresses required to access system memory from a\r
+ Provides the PCI controller-specific addresses required to access system memory from a\r
DMA bus master. \r
\r
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
OUT VOID **Resources\r
);\r
\r
-/** \r
- @par Protocol Description:\r
- Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
- used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
- \r
- @param ParentHandle\r
- The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
-\r
- @param PollMem\r
- Polls an address in memory mapped I/O space until an exit condition is met, \r
- or a timeout occurs. \r
-\r
- @param PollIo\r
- Polls an address in I/O space until an exit condition is met, or a timeout occurs. \r
-\r
- @param Mem.Read\r
- Allows reads from memory mapped I/O space. \r
-\r
- @param Mem.Write\r
- Allows writes to memory mapped I/O space. \r
-\r
- @param Io.Read\r
- Allows reads from I/O space. \r
-\r
- @param Io.Write\r
- Allows writes to I/O space. \r
-\r
- @param Pci.Read\r
- Allows reads from PCI configuration space. \r
-\r
- @param Pci.Write\r
- Allows writes to PCI configuration space. \r
-\r
- @param CopyMem\r
- Allows one region of PCI root bridge memory space to be copied to another \r
- region of PCI root bridge memory space. \r
-\r
- @param Map\r
- Provides the PCI controller's specific addresses needed to access system memory for DMA. \r
-\r
- @param Unmap\r
- Releases any resources allocated by Map(). \r
-\r
- @param AllocateBuffer\r
- Allocates pages that are suitable for a common buffer mapping. \r
-\r
- @param FreeBuffer\r
- Free pages that were allocated with AllocateBuffer(). \r
-\r
- @param Flush\r
- Flushes all PCI posted write transactions to system memory. \r
-\r
- @param GetAttributes\r
- Gets the attributes that a PCI root bridge supports setting with SetAttributes(), \r
- and the attributes that a PCI root bridge is currently using. \r
-\r
- @param SetAttributes\r
- Sets attributes for a resource range on a PCI root bridge. \r
-\r
- @param Configuration\r
- Gets the current resource settings for this PCI root bridge. \r
-\r
- @param SegmentNumber\r
- The segment number that this PCI root bridge resides.\r
-\r
-**/\r
+///\r
+/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
+/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
+///\r
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
+ ///\r
+ /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
+ ///\r
EFI_HANDLE ParentHandle;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;\r
+ \r
+ ///\r
+ /// The segment number that this PCI root bridge resides.\r
+ ///\r
UINT32 SegmentNumber;\r
};\r
\r
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