/** @file\r
- PCI Root Bridge I/O protocol as defined in the EFI 1.1 specification.\r
+ PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.\r
\r
PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
- defferent types of bus mastering DMA\r
+ defferent types of bus mastering DMA.\r
\r
- Copyright (c) 2006, Intel Corporation \r
+ Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
- Module Name: PciRootBridgeIo.h\r
-\r
**/\r
\r
#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
\r
typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
+///\r
typedef enum {\r
EfiPciWidthUint8,\r
EfiPciWidthUint16,\r
EfiPciWidthMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
\r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
+/// *******************************************************\r
+///\r
typedef enum {\r
+ ///\r
+ /// A read operation from system memory by a bus master that is not capable of producing\r
+ /// PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterRead,\r
+ ///\r
+ /// A write operation from system memory by a bus master that is not capable of producing\r
+ /// PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterWrite,\r
+ ///\r
+ /// Provides both read and write access to system memory by both the processor and a bus\r
+ /// master that is not capable of producing PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterCommonBuffer,\r
+ ///\r
+ /// A read operation from system memory by a bus master that is capable of producing PCI\r
+ /// dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterRead64,\r
+ ///\r
+ /// A write operation to system memory by a bus master that is capable of producing PCI\r
+ /// dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterWrite64,\r
+ ///\r
+ /// Provides both read and write access to system memory by both the processor and a bus\r
+ /// master that is capable of producing PCI dual address cycles.\r
+ ///\r
EfiPciOperationBusMasterCommonBuffer64,\r
EfiPciOperationMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
);\r
\r
typedef struct {\r
+ ///\r
+ /// Read PCI controller registers in the PCI root bridge memory space.\r
+ ///\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;\r
+ ///\r
+ /// Write PCI controller registers in the PCI root bridge memory space.\r
+ ///\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 DestAddress,\r
);\r
\r
/** \r
- Provides the PCI controller-Cspecific addresses required to access system memory from a\r
+ Provides the PCI controller-specific addresses required to access system memory from a\r
DMA bus master. \r
\r
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
IN VOID *HostAddress,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN VOID *Mapping\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_ALLOCATE_TYPE Type,\r
IN EFI_MEMORY_TYPE MemoryType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN UINTN Pages,\r
IN VOID *HostAddress\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
OUT UINT64 *Supports,\r
OUT UINT64 *Attributes\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN UINT64 Attributes,\r
IN OUT UINT64 *ResourceBase,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
OUT VOID **Resources\r
);\r
\r
+///\r
+/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
+/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
+///\r
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
+ ///\r
+ /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
+ ///\r
EFI_HANDLE ParentHandle;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;\r
+ \r
+ ///\r
+ /// The segment number that this PCI root bridge resides.\r
+ ///\r
UINT32 SegmentNumber;\r
};\r
\r
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