Update the copyright notice format

[mirror_edk2.git] / MdePkg / Include / Protocol / PciRootBridgeIo.h

diff --git a/MdePkg/Include/Protocol/PciRootBridgeIo.h b/MdePkg/Include/Protocol/PciRootBridgeIo.h
index b3dbfa9cab641d83dcc50a2d236f2ece2fa76dd9..8c66bed4cc936e602ee0faa021cd8f37c63ad7f3 100644 (file)
--- a/MdePkg/Include/Protocol/PciRootBridgeIo.h
+++ b/MdePkg/Include/Protocol/PciRootBridgeIo.h
@@ -3,10 +3,10 @@
 \r
   PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
   and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
-  defferent types of bus mastering DMA\r
+  defferent types of bus mastering DMA.\r
 \r
-  Copyright (c) 2006, Intel Corporation                                                         \r
-  All rights reserved. This program and the accompanying materials                          \r
+  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
   http://opensource.org/licenses/bsd-license.php                                            \r
@@ -19,8 +19,6 @@
 #ifndef __PCI_ROOT_BRIDGE_IO_H__\r
 #define __PCI_ROOT_BRIDGE_IO_H__\r
 \r
-#include <PiDxe.h>\r
-\r
 #define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
   { \\r
     0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
@@ -28,6 +26,11 @@
 \r
 typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
 \r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
+///\r
 typedef enum {\r
   EfiPciWidthUint8,\r
   EfiPciWidthUint16,\r
@@ -44,12 +47,41 @@ typedef enum {
   EfiPciWidthMaximum\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
 \r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
+/// *******************************************************\r
+///\r
 typedef enum {\r
+  ///\r
+  /// A read operation from system memory by a bus master that is not capable of producing\r
+  /// PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterRead,\r
+  ///\r
+  /// A write operation from system memory by a bus master that is not capable of producing\r
+  /// PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterWrite,\r
+  ///\r
+  /// Provides both read and write access to system memory by both the processor and a bus\r
+  /// master that is not capable of producing PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterCommonBuffer,\r
+  ///\r
+  /// A read operation from system memory by a bus master that is capable of producing PCI\r
+  /// dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterRead64,\r
+  ///\r
+  /// A write operation to system memory by a bus master that is capable of producing PCI\r
+  /// dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterWrite64,\r
+  ///\r
+  /// Provides both read and write access to system memory by both the processor and a bus\r
+  /// master that is capable of producing PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterCommonBuffer64,\r
   EfiPciOperationMaximum\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
@@ -137,7 +169,13 @@ EFI_STATUS
   );\r
 \r
 typedef struct {\r
+  ///\r
+  /// Read PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Read;\r
+  ///\r
+  /// Write PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
 \r
@@ -167,7 +205,7 @@ EFI_STATUS
   );\r
 \r
 /**                                                                 \r
-  Provides the PCI controller-Cspecific addresses required to access system memory from a\r
+  Provides the PCI controller-specific addresses required to access system memory from a\r
   DMA bus master.                                                                        \r
             \r
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@@ -360,7 +398,14 @@ EFI_STATUS
   OUT VOID                                     **Resources\r
   );\r
 \r
+///\r
+/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
+/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
+///\r
 struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
+  ///\r
+  /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
+  ///\r
   EFI_HANDLE                                      ParentHandle;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollMem;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollIo;\r
@@ -376,6 +421,10 @@ struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES  GetAttributes;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES  SetAttributes;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION   Configuration;\r
+  \r
+  ///\r
+  /// The segment number that this PCI root bridge resides.\r
+  ///\r
   UINT32                                          SegmentNumber;\r
 };\r
 \r