Add the detailed descriptions for the structure data member in these protocol.

[mirror_edk2.git] / MdePkg / Include / Protocol / PciRootBridgeIo.h

diff --git a/MdePkg/Include/Protocol/PciRootBridgeIo.h b/MdePkg/Include/Protocol/PciRootBridgeIo.h
index fb17222d3ad488d44b0493fe07757b0bab33f6cd..970aee0642cb07da18eeafe24a3bd8ca21842b96 100644 (file)
--- a/MdePkg/Include/Protocol/PciRootBridgeIo.h
+++ b/MdePkg/Include/Protocol/PciRootBridgeIo.h
@@ -26,6 +26,11 @@
 \r
 typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
 \r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH\r
+/// *******************************************************\r
+///\r
 typedef enum {\r
   EfiPciWidthUint8,\r
   EfiPciWidthUint16,\r
@@ -42,12 +47,41 @@ typedef enum {
   EfiPciWidthMaximum\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;\r
 \r
+///\r
+/// *******************************************************\r
+/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION\r
+/// *******************************************************\r
+///\r
 typedef enum {\r
+  ///\r
+  /// A read operation from system memory by a bus master that is not capable of producing\r
+  /// PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterRead,\r
+  ///\r
+  /// A write operation from system memory by a bus master that is not capable of producing\r
+  /// PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterWrite,\r
+  ///\r
+  /// Provides both read and write access to system memory by both the processor and a bus\r
+  /// master that is not capable of producing PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterCommonBuffer,\r
+  ///\r
+  /// A read operation from system memory by a bus master that is capable of producing PCI\r
+  /// dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterRead64,\r
+  ///\r
+  /// A write operation to system memory by a bus master that is capable of producing PCI\r
+  /// dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterWrite64,\r
+  ///\r
+  /// Provides both read and write access to system memory by both the processor and a bus\r
+  /// master that is capable of producing PCI dual address cycles.\r
+  ///\r
   EfiPciOperationBusMasterCommonBuffer64,\r
   EfiPciOperationMaximum\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
@@ -135,7 +169,13 @@ EFI_STATUS
   );\r
 \r
 typedef struct {\r
+  ///\r
+  /// Read PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Read;\r
+  ///\r
+  /// Write PCI controller registers in the PCI root bridge memory space.\r
+  ///\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;\r
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
 \r
@@ -358,73 +398,14 @@ EFI_STATUS
   OUT VOID                                     **Resources\r
   );\r
 \r
-/**  \r
-  @par Protocol Description:\r
-  Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
-  used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
-  \r
-  @param ParentHandle\r
-  The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
-\r
-  @param PollMem\r
-  Polls an address in memory mapped I/O space until an exit condition is met, \r
-  or a timeout occurs. \r
-\r
-  @param PollIo\r
-  Polls an address in I/O space until an exit condition is met, or a timeout occurs. \r
-\r
-  @param Mem.Read\r
-  Allows reads from memory mapped I/O space. \r
-\r
-  @param Mem.Write\r
-  Allows writes to memory mapped I/O space. \r
-\r
-  @param Io.Read\r
-  Allows reads from I/O space. \r
-\r
-  @param Io.Write\r
-  Allows writes to I/O space. \r
-\r
-  @param Pci.Read\r
-  Allows reads from PCI configuration space. \r
-\r
-  @param Pci.Write\r
-  Allows writes to PCI configuration space. \r
-\r
-  @param CopyMem\r
-  Allows one region of PCI root bridge memory space to be copied to another \r
-  region of PCI root bridge memory space. \r
-\r
-  @param Map\r
-  Provides the PCI controller's specific addresses needed to access system memory for DMA. \r
-\r
-  @param Unmap\r
-  Releases any resources allocated by Map(). \r
-\r
-  @param AllocateBuffer\r
-  Allocates pages that are suitable for a common buffer mapping. \r
-\r
-  @param FreeBuffer\r
-  Free pages that were allocated with AllocateBuffer(). \r
-\r
-  @param Flush\r
-  Flushes all PCI posted write transactions to system memory. \r
-\r
-  @param GetAttributes\r
-  Gets the attributes that a PCI root bridge supports setting with SetAttributes(), \r
-  and the attributes that a PCI root bridge is currently using. \r
-\r
-  @param SetAttributes\r
-  Sets attributes for a resource range on a PCI root bridge. \r
-\r
-  @param Configuration\r
-  Gets the current resource settings for this PCI root bridge. \r
-\r
-  @param SegmentNumber\r
-  The segment number that this PCI root bridge resides.\r
-\r
-**/\r
+///\r
+/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
+/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
+///\r
 struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
+  ///\r
+  /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
+  ///\r
   EFI_HANDLE                                      ParentHandle;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollMem;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM     PollIo;\r
@@ -440,6 +421,10 @@ struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES  GetAttributes;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES  SetAttributes;\r
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION   Configuration;\r
+  \r
+  ///\r
+  /// The segment number that this PCI root bridge resides.\r
+  ///\r
   UINT32                                          SegmentNumber;\r
 };\r
 \r