/** @file\r
- PCI Root Bridge I/O protocol as defined in the EFI 1.1 specification.\r
+ PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.\r
\r
PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, \r
and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform \r
defferent types of bus mastering DMA\r
\r
- Copyright (c) 2006, Intel Corporation \r
+ Copyright (c) 2006 - 2008, Intel Corporation \r
All rights reserved. This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
- Module Name: PciRootBridgeIo.h\r
-\r
**/\r
\r
#ifndef __PCI_ROOT_BRIDGE_IO_H__\r
#define __PCI_ROOT_BRIDGE_IO_H__\r
\r
+#include <PiDxe.h>\r
+\r
#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \\r
{ \\r
0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 DestAddress,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
IN VOID *HostAddress,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN VOID *Mapping\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_ALLOCATE_TYPE Type,\r
IN EFI_MEMORY_TYPE MemoryType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN UINTN Pages,\r
IN VOID *HostAddress\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
OUT UINT64 *Supports,\r
OUT UINT64 *Attributes\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN UINT64 Attributes,\r
IN OUT UINT64 *ResourceBase,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION) (\r
+(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
OUT VOID **Resources\r
);\r
\r
+/** \r
+ @par Protocol Description:\r
+ Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are \r
+ used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. \r
+ \r
+ @param ParentHandle\r
+ The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
+\r
+ @param PollMem\r
+ Polls an address in memory mapped I/O space until an exit condition is met, \r
+ or a timeout occurs. \r
+\r
+ @param PollIo\r
+ Polls an address in I/O space until an exit condition is met, or a timeout occurs. \r
+\r
+ @param Mem.Read\r
+ Allows reads from memory mapped I/O space. \r
+\r
+ @param Mem.Write\r
+ Allows writes to memory mapped I/O space. \r
+\r
+ @param Io.Read\r
+ Allows reads from I/O space. \r
+\r
+ @param Io.Write\r
+ Allows writes to I/O space. \r
+\r
+ @param Pci.Read\r
+ Allows reads from PCI configuration space. \r
+\r
+ @param Pci.Write\r
+ Allows writes to PCI configuration space. \r
+\r
+ @param CopyMem\r
+ Allows one region of PCI root bridge memory space to be copied to another \r
+ region of PCI root bridge memory space. \r
+\r
+ @param Map\r
+ Provides the PCI controller's specific addresses needed to access system memory for DMA. \r
+\r
+ @param Unmap\r
+ Releases any resources allocated by Map(). \r
+\r
+ @param AllocateBuffer\r
+ Allocates pages that are suitable for a common buffer mapping. \r
+\r
+ @param FreeBuffer\r
+ Free pages that were allocated with AllocateBuffer(). \r
+\r
+ @param Flush\r
+ Flushes all PCI posted write transactions to system memory. \r
+\r
+ @param GetAttributes\r
+ Gets the attributes that a PCI root bridge supports setting with SetAttributes(), \r
+ and the attributes that a PCI root bridge is currently using. \r
+\r
+ @param SetAttributes\r
+ Sets attributes for a resource range on a PCI root bridge. \r
+\r
+ @param Configuration\r
+ Gets the current resource settings for this PCI root bridge. \r
+\r
+ @param SegmentNumber\r
+ The segment number that this PCI root bridge resides.\r
+\r
+**/\r
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {\r
EFI_HANDLE ParentHandle;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
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