**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_CHIP_SELECT) (\r
+(EFIAPI *EFI_SPI_CHIP_SELECT)(\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN BOOLEAN PinValue\r
);\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_CLOCK) (\r
+(EFIAPI *EFI_SPI_CLOCK)(\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN UINT32 *ClockHz\r
);\r
///\r
/// A Unicode string specifying the SPI chip vendor.\r
///\r
- CONST CHAR16 *Vendor;\r
+ CONST CHAR16 *Vendor;\r
\r
///\r
/// A Unicode string specifying the SPI chip part number.\r
///\r
- CONST CHAR16 *PartNumber;\r
+ CONST CHAR16 *PartNumber;\r
\r
///\r
/// The minimum SPI bus clock frequency used to access this chip. This value\r
/// may be specified in the chip's datasheet. If not, use the value of zero.\r
///\r
- UINT32 MinClockHz;\r
+ UINT32 MinClockHz;\r
\r
///\r
/// The maximum SPI bus clock frequency used to access this chip. This value\r
/// is found in the chip's datasheet.\r
///\r
- UINT32 MaxClockHz;\r
+ UINT32 MaxClockHz;\r
\r
///\r
/// Specify the polarity of the chip select pin. This value can be found in\r
/// the SPI chip's datasheet. Specify TRUE when a one asserts the chip select\r
- ///and FALSE when a zero asserts the chip select.\r
+ /// and FALSE when a zero asserts the chip select.\r
///\r
- BOOLEAN ChipSelectPolarity;\r
+ BOOLEAN ChipSelectPolarity;\r
} EFI_SPI_PART;\r
\r
///\r
///\r
/// A Unicode string describing the SPI bus\r
///\r
- CONST CHAR16 *FriendlyName;\r
+ CONST CHAR16 *FriendlyName;\r
\r
///\r
/// Address of the first EFI_SPI_PERIPHERAL data structure connected to this\r
/// bus. Specify NULL if there are no SPI peripherals connected to this bus.\r
///\r
- CONST EFI_SPI_PERIPHERAL *Peripherallist;\r
+ CONST EFI_SPI_PERIPHERAL *Peripherallist;\r
\r
///\r
/// Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely\r
/// describes the SPI controller.\r
///\r
- CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;\r
+ CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;\r
\r
///\r
/// Address of the routine which controls the clock used by the SPI bus for\r
/// this SPI peripheral. The SPI host co ntroller's clock routine is called\r
/// when this value is set to NULL.\r
///\r
- EFI_SPI_CLOCK Clock;\r
+ EFI_SPI_CLOCK Clock;\r
\r
///\r
/// Address of a data structure containing the additional values which\r
/// host's SPI controller driver. When Clock is not NULL, the declaration for\r
/// this data structure is provided by the board layer.\r
///\r
- VOID *ClockParameter;\r
+ VOID *ClockParameter;\r
} EFI_SPI_BUS;\r
\r
///\r
/// Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if\r
/// the current data structure is the last one on the SPI bus.\r
///\r
- CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;\r
\r
///\r
/// A unicode string describing the function of the SPI part.\r
///\r
- CONST CHAR16 *FriendlyName;\r
+ CONST CHAR16 *FriendlyName;\r
\r
///\r
/// Address of a GUID provided by the vendor of the SPI peripheral driver.\r
/// This reduces the comparison logic in the SPI peripheral driver's\r
/// Supported routine.\r
///\r
- CONST GUID *SpiPeripheralDriverGuid;\r
+ CONST GUID *SpiPeripheralDriverGuid;\r
\r
///\r
/// The address of an EFI_SPI_PART data structure which describes this chip.\r
///\r
- CONST EFI_SPI_PART *SpiPart;\r
+ CONST EFI_SPI_PART *SpiPart;\r
\r
///\r
/// The maximum clock frequency is specified in the EFI_SPI_P ART. When this\r
/// this value is non-zero and less than the value in the EFI_SPI_PART then\r
/// this value is used for the maximum clock frequency for the SPI part.\r
///\r
- UINT32 MaxClockHz;\r
+ UINT32 MaxClockHz;\r
\r
///\r
/// Specify the idle value of the clock as found in the datasheet.\r
/// Use zero (0) if the clock'S idle value is low or one (1) if the the\r
/// clock's idle value is high.\r
///\r
- BOOLEAN ClockPolarity;\r
+ BOOLEAN ClockPolarity;\r
\r
///\r
/// Specify the clock delay after chip select. Specify zero (0) to delay an\r
/// entire clock cycle or one (1) to delay only half a clock cycle.\r
///\r
- BOOLEAN ClockPhase;\r
+ BOOLEAN ClockPhase;\r
\r
///\r
/// SPI peripheral attributes, select zero or more of:\r
/// * SPI_PART_SUPPORTS_4_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to\r
/// support a 4-bit data bus\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
\r
///\r
/// Address of a vendor specific data structure containing additional board\r
/// configuration details related to the SPI chip. The SPI peripheral layer\r
/// uses this data structure when configuring the chip.\r
///\r
- CONST VOID *ConfigurationData;\r
+ CONST VOID *ConfigurationData;\r
\r
///\r
/// The address of an EFI_SPI_BUS data structure which describes the SPI bus\r
/// to which this chip is connected.\r
///\r
- CONST EFI_SPI_BUS *SpiBus;\r
+ CONST EFI_SPI_BUS *SpiBus;\r
\r
///\r
/// Address of the routine which controls the chip select pin for this SPI\r
/// peripheral. Call the SPI host controller's chip select routine when this\r
/// value is set to NULL.\r
///\r
- EFI_SPI_CHIP_SELECT ChipSelect;\r
+ EFI_SPI_CHIP_SELECT ChipSelect;\r
\r
///\r
/// Address of a data structure containing the additional values which\r
/// control. When Chipselect is not NULL, the declaration for this data\r
/// structure is provided by the board layer.\r
///\r
- VOID *ChipSelectParameter;\r
+ VOID *ChipSelectParameter;\r
};\r
\r
///\r
///\r
/// The number of SPI busses on the board.\r
///\r
- UINT32 BusCount;\r
+ UINT32 BusCount;\r
\r
///\r
/// The address of an array of EFI_SPI_BUS data structure addresses.\r
///\r
- CONST EFI_SPI_BUS *CONST *CONST Buslist;\r
+ CONST EFI_SPI_BUS *CONST *CONST Buslist;\r
} EFI_SPI_CONFIGURATION_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSpiConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiSpiConfigurationProtocolGuid;\r
\r
#endif // __SPI_CONFIGURATION_PROTOCOL_H__\r
projects / mirror_edk2.git / blobdiff